Telefonaktiebolaget Lm Ericsson (publ)

Peter Svensson

Magnus Nilsson

Torsten John Carlsson

Peter Jakobsson

Martin Isberg

Dandan Hao

Per Ingelhag

Joakim Plahn

Sten Wallin

Agneta Ljungbro

Bengt Wikenfalk

Mikael Lostedt

Örjan Renström

In an example embodiment, a system comprises a chain of serially coupled nodes, including a central processing node (CPN) and one or more radio communications nodes (RCNs). The CPN couples to a first RCN in the chain via a dielectric waveguide (DWG) link and any further RCNs in the chain are successively connected in serial fashion from the first RCN via further (DWG) links. The CPN generates outbound radio carrier signals that are waveguide-propagated in a downstream direction of the chain, for over-the-air (OTA) by targeted ones of the RCNs, while radio carrier signals received via OTA reception by respective ones of the RCNs are waveguide propagated as inbound radio signals in an upstream direction of the chain, for processing by the CPN. Advantages from he contemplated system include greatly simplified implementation of the RCNs, with lower cost and power consumption. Further, strategic placement of failover CPNs and DWG links provide for continued operation in the face of CPN or DWG link failures.

Method and apparatus for radio communications

A method, performed in a debug host, for observing software execution on a computer having one or more processor cores, a cache attached to the one or more processor cores via respective execution pipelines forming a cache arrangement, and a memory, comprises obtaining an instruction trace of the cache arrangement and a data trace for data being loaded from the memory into the cache. The instruction trace is synchronized with the data trace to generate a synchronized data trace and/or a synchronized instruction trace. A state of a memory model, representing a memory readable by the one or more processor cores via a respective instruction is updated using the synchronized data trace and the synchronized instruction trace.

Observation by a debug host with memory model and timing offset calculation between instruction and data traces of software execution carried on in a debug target having a main memory and a cache arrangement

Secured debug of an integrated circuit having a test operation mode and a secure mission operation mode. The integrated circuit has a processing unit, a test interface through which the test operation mode is controllable, an on-chip memory which is accessible in the test operation mode and in the secure mission operation mode, and one or more protected resources inaccessible in the test operation mode. The processing unit is configured, in the test operation mode, to receive an authenticated object through the test interface, and store the received authenticated object in the on-chip memory. The processing unit is moreover configured, upon reset into the secure mission operation mode, to execute a boot procedure to determine that the authenticated object is available in the on-chip memory, authenticate the authenticated object, and&#x2014;upon successful authentication&#x2014;render the more protected resources accessible to a debug host external to the integrated circuit.

Enabling secured debug of an integrated circuit

Growing community of inventors

Lund, Sweden

Peter Svensson