Infineon Technologies Ag

Infineon Technologies Austria Ag

Peter Strobel

Jens G Pohl

Michael Bauer

Edward Fuergut

Holger Woerner

Ludwig Heitzer

Simon Jerebic

Christian Stuempfl

Joachim Mahler

Robert-Christian Hagen

Bernd Goller

Thorsten Meyer

Hermann Vilsmeier

Giovanni Ragasa Garbin

Chen Wen Lee

Benjamin Reichert

Martin Gruber

Thorsten Scharf

Rainer Steiner

Heinz Pape

Bernhard Zuhr

Ulrich Bachmaier

Rudolf Kerler

Wolfram Eurskens

Frank Singer

Alexander Heinrich

Markus Brunnbauer

Gerald Ofner

Irmgard Escher-Poeppel

Thomas Bemmerl

Daniel Porwol

Ulrich Wachter

Thomas Behrens

Konrad Roesl

Stephan Stoeckl

Gerold Gruendler

Bernd Rakow

Stefan Woetzel

Rupert Fischer

Markus Fink

Edward Fürgut

Robert Christian Hagen

Eric Kuerzel

A package is disclosed. In one example, the package comprises a substrate having at least one first recess on a front side and at least one second recess on a back side, wherein the substrate is separated into a plurality of separate substrate sections by the at least one first recess and the at least one second recess, an electronic component mounted on the front side of the substrate, and a single encapsulant filling at least part of the at least one first recess and at least part of the at least one second recess. The encapsulant fully circumferentially surrounds sidewalls of at least one of the substrate sections.

Package with separate substrate sections

A method of mounting electronic components on one or more carrier bodies is disclosed. The method comprises providing a support body with at least one first alignment mark, mounting the one or more carrier bodies, each having at least one second alignment mark, on the support body by alignment between the at least one first alignment mark and the at least one second alignment mark. Thereafter, the method includes mounting the plurality of electronic components on a respective one of the one or more carrier bodies by alignment using the at least one second alignment mark.

Processing of one or more carrier bodies and electronic components by multiple alignment

A semiconductor device includes a carrier, a power semiconductor die that includes first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively, a die attach material arranged between the carrier and the first electrode, wherein the die attach material forms a fillet at the side surface of the power semiconductor die, wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die, wherein the height of the power semiconductor die is a length of the side surface, and wherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers.

Die attach methods and semiconductor devices manufactured based on such methods

A method includes providing a carrier, depositing a die attach material on the carrier, and arranging a semiconductor die on the die attach material, wherein a main surface of the semiconductor die facing the die attach material at least partly contacts the die attach material, wherein immediately after arranging the semiconductor die on the die attach material, a first maximum extension of the die attach material over edges of the main surface is less than about 100 micrometers.

A semiconductor device includes a carrier, a semiconductor die and a die attach material arranged between the carrier and the semiconductor die. A fillet height of the die attach material is less than about 95% of a height of the semiconductor die. A maximum extension of the die attach material over edges of a main surface of the semiconductor die facing the die attach material is less than about 200 micrometers.

Methods for connecting chips to a chip carrier are disclosed. In some embodiments the method for connecting a plurality of chips to a chip carrier includes placing first chips on a transfer carrier, placing second chips on the transfer carrier, placing the transfer carrier with the first and second chips on the chip carrier and forming connections between the first chips and the chip carrier and the second chips and the chip carrier.

Batch process for connecting chips to a carrier

A chip arrangement is provided which comprises a carrier; and at least two chips arranged over the carrier; wherein a continuous insulating layer is arranged between the at least two chips and between the carrier and at least one of the at least two chips.

Chip arrangement and method of manufacturing the same

A method of manufacturing semiconductor device comprises placing multiple chips onto a carrier. An encapsulation material is applied to the multiple chips and the carrier for forming an encapsulation workpiece. The encapsulation workpiece having a first main face facing the carrier and a second main face opposite to the first main face. Further, marking elements are applied to the encapsulation workpiece relative to the multiple chips, the marking elements being detectable on the first main face and on the second main face.

Reconfigured wafer alignment

A plastic housing includes plastic external faces and the underside of the plastic housing comprises external contact areas on which external contacts are arranged. The plastic external faces are covered by a closed metal layer apart from the underside, wherein the boundary layer between plastic external faces and the closed metal layer includes exposed electrically conductive inclusions of the plastic of the housing.

Plastic housing and semiconductor component with said plastic housing

An external contact material for external contacts of a semiconductor device and a method for producing the same are described. The external contact material includes a lead-free solder material. Provided in the solder material is a filler which forms a plurality of gas pores and/or has plastic particles which are arranged in the volume of the solder material.

External contact material for external contacts of a semiconductor device and method of making the same

A semiconductor component includes a plastic housing including: plastic outer surfaces; lower outer contact surfaces arranged on an underside of the housing; upper outer contact surfaces arranged on a top side of the housing that is opposite the underside; and outer interconnects electrically connecting the lower outer contact surfaces to the upper outer contact surfaces, the outer interconnects including a layer of solder arranged on conduction paths along an outer contour of the housing.

Semiconductor component with plastic housing, and process for producing the same

A semiconductor device with a thinned semiconductor chip and a method for producing the latter is disclosed. In one embodiment, the thinned semiconductor chip has a top side with contact areas and a rear side with a rear side electrode. In this case, the rear side electrode is cohesively connected to a chip pad of a circuit carrier via an electrically conductive layer. In another embodiment, the thinned semiconductor chips of this semiconductor device according to the invention have low-microdefect edge side regions with semiconductor element structures and edge sides patterned by etching technology.

Semiconductor device with a thinned semiconductor chip and method for producing the thinned semiconductor chip

A sensor component and a panel used for the production thereof is disclosed. The sensor component has, in addition to a sensor chip with a sensor region, a rear side and passive components. These are embedded jointly in a plastics composition, in such a way that their respective electrodes can be wired from an overall top side of a plastic plate.

Sensor component and panel used for the production thereof

An electronic circuit in a package-on-package configuration includes: a lower subassembly with a first electronic element, a first wiring carrier, a first housing with a first redistribution layer and an arrangement of solder balls disposed on the first redistribution layer and an upper subassembly with a second electronic element mounted on the lower subassembly. A method for producing the electronic circuit in a package-on-package configuration includes: adhering an upper side of the first electronic element to an underside of the first redistribution layer via a radiation-crosslinking thermoplastic adhesive.

Electronic circuit in a package-on-package configuration and method for producing the same

An electronic module and a method for the production thereof is disclosed. In one embodiment, the electronic module has a plurality of components arranged on a wiring block. The wiring block has a plurality of outer sides and has in its volume lines interconnecting contact pads on the outer sides. The contact pads are electrically connected to component connections of the components.

Growing community of inventors

Wuppertal, Germany

Peter Strobel