Siltronic Ag

Intel Corporation

Imec Vzw

Wacker Siltronic Gesellschaft F&uuml;r Halbleiter Materialien Ag

Ihp, Gmbh

Peter Storck

Wolfgang Siebert

Norbert Werner

Thomas Schroeder

Sarad Bahadur Thapa

Martin Vorderwestner

Hans Joachim Muessig

Wilfried Von Ammon

Peter G Tolchinsky

Reinhard Schauer

Thomas Buschhardt

Irwin Yablok

Ming Zhao

Helmut Schwenk

Klaus Messmann

Hans-Joachim Müssig

Frank Muemmler

R&uuml;diger Schmolke

Dieter Gr&auml;f

Michael Boy

Ludwig Koester

Ruediger Schmolke

G&uuml;nther Obermeier

Ute Rothammer

Peter Dreier

Rudolf Mayrhuber

Lucas Becker

Elena Soyka

Guenter Sachs

Thomas Schröder

Frank Mümmler

Günter Sachs

A method heteroepitaxially deposits a silicon germanium layer on a substrate. The silicon germanium layer has a composition SiGe, where 0.01≤x≤1. The substrate is a silicon single crystal wafer or a silicon-on-insulator wafer. The method includes: providing a mask layer atop the substrate; removing the mask layer in an edge region of the substrate to provide access to an annular-shaped free surface of the substrate in the edge region of the substrate surrounding a remainder of the mask layer; depositing an edge reservoir consisting of a relaxed or partially relaxed silicon germanium layer atop the annular-shaped free surface of the substrate; removing the remainder of the mask layer; and depositing the silicon germanium layer atop the substrate and atop the edge reservoir, the silicon germanium layer contacting an inner lateral surface of the edge reservoir.

Method for depositing a silicon germanium layer on a substrate

Suitability of silicon wafers for use in device processing without generation of fatal defects is assessed by using SIRD to measure stress in a wafer cut from a piece of a crystal ingot after first and second thermal treatments of the water, the second thermal treatment consisting of a heating phase, a holding phase, and a cooling phase. The result is used to consider whether silicon wafers cut from the piece can adequately survive device processing without generating excess defects.

Method for producing semiconductor wafers

A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant adetermined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a&#x3e;a, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from &#x2212;50 &#x3bc;m to 50 &#x3bc;m.

Layered semiconductor substrate with reduced bow having a group III nitride layer and method for manufacturing it

A semiconductor wafer has a silicon single crystal substrate having a top surface and a stack of layers covering the top surface, the stack of layers containing an AlN nucleation layer covering the top surface of the silicon single crystal substrate, wherein the top surface of the silicon single crystal substrate has a crystal lattice orientation which is off-oriented with respect to the {111}-plane, the normal to the top surface being inclined with respect to the &#x3c;111&#x3e;-direction toward the &#x3c;11-2&#x3e;-direction by an angle &#x3b8; of not less than 0.3&#xb0; and not more than 6&#xb0;, the azimuthal tolerance of the inclination being &#xb1;0.1&#xb0;; and an AlGaN buffer layer which covers the AlN nucleation layer and contains one or more AlGaN layers, wherein 0&#x3c;&#xd7;&#x3c;1.

Semiconductor wafer and a method for producing the semiconductor wafer

An epitaxial wafer comprises a silicon substrate wafer having first and second sides, and a silicon epitaxial layer deposited on the first side, and optionally one or more additional epitaxial layers on top of the silicon epitaxial layer, at least one of the silicon epitaxial layer or at least one of the one or more additional epitaxial layers being doped with nitrogen at a concentration of 1&#xd7;10atoms/cmor more and 1&#xd7;10atoms/cmor less. The epitaxial wafer is produced by depositing the silicon epitaxial layer and/or at least one of the one or more additional epitaxial layers, at a deposition temperature of 940&#xb0; C. or less through chemical vapor deposition in the presence of a deposition gas atmosphere containing one or more silicon precursor compounds and one or more nitrogen precursor compounds.

Epitaxial wafer and a method of manufacturing thereof

SOI wafers are manufactured by forming on a silicon substrate a monocrystalline first, cubic 1a-3 metal or mixed metal oxide layer whose lattice constant differs from that of the substrate by 5% or less; forming a second cubic 1a-3 mixed metal oxide layer having a lattice constant within 2% of the lattice constant of the first metal or mixed metal oxide layer, and having a graded metal content to vary the lattice content in the second mixed metal oxide layer from that of the first layer, and thermally treating the layered product in an oxygen atmosphere to form an amorphous interlayer between the substrate and the first metal or mixed metal oxide layer.

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A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate.

Semiconductor wafer with a heteroepitaxial layer and a method for producing the wafer

A method for producing a wafer with a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side, the method using steps in the following order:

Method for producing a wafer comprising a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side

A layered semiconductor wafer contains the following layers in the given order:

Semiconductor wafer and process for its production

A multilayer structure, comprises a substrate and a layer of silicon and germanium (SiGe layer) deposited heteroepitaxially thereon having the composition SiGeand having a lattice constant which differs from the lattice constant of silicon, and a thin interfacial layer deposited on the SiGe layer and having the composition SiGe, which thin interfacial layer binds threading dislocations, and at least one further layer deposited on the interfacial layer.

Multilayer structure comprising a substrate and a layer of silicon and germanium deposited heteroepitaxially thereon, and a process for producing it

A semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface, wherein the surface of the epitaxial layer has a maximum density of 0.14 localized light scatterers per cmwith a cross section of greater than or equal to 0.12 &#x3bc;m, and the front surface of the semiconductor wafer, prior to the deposition of the epitaxial layer, has a surface roughness of 0.05 to 0.29 nm RMS, measured by AFM on a 1 &#x3bc;m&#xd7;1 &#x3bc;m reference area. There is also a process for producing a semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface. The process includes the following: (a) a stock removal polishing step as the only polishing step; (b) cleaning and drying of the semiconductor wafer; (c) pretreatment of the front surface of the semiconductor wafer at a temperature of from 950 to 1250 degrees Celsius in an epitaxy reactor; and (d) deposition of the epitaxial layer on the front surface of the pretreated semiconductor wafer.

Epitaxially coated semiconductor wafer and process for producing it

A process for epitaxially coating the front surface of a semiconductor wafer in a CVD reactor, the front surface of the semiconductor wafer being exposed to a process gas which contains a source gas and a carrier gas, and the back surface of the semiconductor wafer being exposed to a displacement gas, wherein the displacement gas contains no more than 5% by volume of hydrogen, with the result that diffusion of dopants out of the back surface of the semiconductor wafer, which is intensified by hydrogen, is substantially avoided. With this process, it is possible to produce a semiconductor wafer with a substrate resistivity of &#x2266;100 m&#x3a9;cm and a resistivity of the epitaxial layer of &#x3e;1 &#x3a9;cm without back-surface coating, the epitaxial layer of which semiconductor wafer has a resistance inhomogeneity of &#x3c;10%.

Process and apparatus for epitaxially coating a semiconductor wafer and epitaxially coated semiconductor wafer

Method for the production of an epitaxially grown semiconductor wafer

Growing community of inventors

Burghausen, Germany

Peter Storck