International Business Machines Corporation

Peter Steven Lenk

Michael John Mayfield

Michael Thomas Vaden

Dung Q Nguyen

William Elton Burky

Robert J Reese

Sanjay Raghunath Deshpande

Shih-Hsiung Stephen Tung

David Andrew Schroter

Improved administering of shared resources in a computer system. In a preferred embodiment, transaction throughput is improved and potential starvation eliminated by a ticket mechanism. The ticket mechanism provides a wait counter and a service counter. When a requested transaction fails, a wait counter is incremented and a wait value is sent to the requesting transaction source. As transactions are completed at the resource, the service counter is incremented and its value broadcast to transaction sources sharing that resource. When a source holds a wait count value that equals the service count value, the source can retry the transaction successfully.

Ticket mechanism for sharing computer resources

A distributed system structure for a large-way, multi-bus, multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. The system allows for the implementation of a bus protocol that reports the state of a cache line to a master device along with the first beat of data delivery for a cacheable coherent Read. Since the achievement of coherency is distributed in time and space, the issue of data integrity is addressed through a variety of actions. In one implementation, the node controller helps to maintain cache coherency for commands by blocking a master device from receiving certain transactions so as to prevent Read-Read deadlocks. In another implementation, the master devices use a bus protocol that prevents Read-Read deadlocks in a distributed, multi-bus, multiprocessor system.

Method and system for implementing remstat protocol under inclusion and non-inclusion of L1 data in L2 cache to prevent read-read deadlock

A method and system for improving pre-fetch accuracy in a data processing system utilizing a pre-fetch history table is disclosed. The method compares a portion of an instruction address to an address located as an entry in a pre-fetch history table based on the status of a validity bit contained in the entry. If the validity bit is set and the addresses match, an indicator field within the entry is checked to see if it is equal to or greater than a threshold level. When the indicator field is greater than the threshold level, a target operand address is pre-fetched based on stride and direction.

Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold

In a multiprocessor system, when a store request has stalled, a signal is generated and sent to all processors indicating such a stalled store situation. In response, all processors will postpone the sending of load, or read, requests to memory until the stalled store request has completed.

Multiprocessor stalled store detection

A method and system according to the present invention of accessing data in a multiprocessor system including a plurality of processors and a memory, wherein the memory includes a plurality of memory locations, and wherein at least a first processor and a second processor each include a reservation indicator and a cache, each cache having a plurality of cache memory locations corresponding to the memory locations. The method and system comprises providing a Load And Reserve request from the first processor for at least one of the plurality of memory locations and determining whether the second processor includes at least one of the plurality of cache memory locations corresponding with the at least one of the memory locations; determining whether the second processor's reservation indicator is set, this determination being in response the second processor including the at least one of the cache memory locations corresponding with the at least one of the memory locations. The method and system also provides a state indicating that the at least one of the cache memory locations of the second processor corresponding to the at least one of the memory locations is invalid, responsive to the reservation indicator not being set.

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Austin, TX, United States of America

Peter Steven Lenk