Siemens Energy & Automation, Inc.

Microchip Technology Inc.

General Instrument Corporation

Siemens Industry, Inc.

Peter Staley

Mario Bilac

David Rich

Carlos Eduardo Restrepo

David Coyne

Hugh T Kinsel

Solomon R Titus

Vaske Mikani

Joselito Endozo

Amit Nayak

In accordance with one aspect the present disclosure is directed toward a method for detecting arc faults on a power line. The method may include monitoring power signals associated with a power line and filtering the power signals to produce a high frequency signal and a low frequency signal. A mask signal may generated based on the low frequency signal, and the high frequency signal may be analyzed to extract a broadband portion of the high frequency signal. A fault counter may be incremented if the magnitude of the broadband portion is approximately greater than a first threshold level. A fault counter may be decremented if the magnitude of the broadband portion is approximately less than the first threshold level. A trip signal is provided to a switching device associated with the power line if the fault counter exceeds a predetermined fault limit.

Systems and methods for arc fault detection

Certain exemplary embodiments can include an arc fault detection circuit. The arc fault detection circuit can include a zero crossing analysis sub-system including a counter configured to determine, for a first waveform, a count of dips that occur between a pair of predetermined zero crossings of a second waveform. The second waveform can be obtained from an electrical circuit.

Systems, devices, and methods for arc fault detection

A circuit breaker system (FIG. ) using electronic trip units is disclosed. The electronic trip units are coupled to a communications bus whereby the electronic trip units can be reconfigured, controlled, and/or monitored by a central computer. Further, the electronic trip units include a data acquisition circuit (FIG. ) that uses chopping to provide better accuracy and increased dynamic range of current measurements.

Data acquisition system for a circuit breaker

A circuit breaker ( ) (FIG. ) has a power line ( ) for carrying a power signal from a source to a load and a current transformer ( ) configured to sense the power signal and provide a sense signal based on the power signal at a first terminal ( ) (FIG. ). The circuit breaker ( ) includes a control circuit ( ) configured to receive a first data message and to provide a second data message based on the first data message at a second terminal ( ). The circuit breaker ( ) further includes a programmable amplifier ( ) coupled to the first terminal ( ) and the second terminal ( ) configured to receive the sense signal, to receive the second data message, to amplify the sense signal based on the second data message, and to provide the amplified sense signal at a third terminal ( ). A method of constructing the circuit breaker ( ) is provided (FIG. ), including providing a circuit breaker ( ) component having a computer-readable indicia ( ) representative of a desired rating of the circuit breaker ( ); coupling an electronic module ( ) to the circuit breaker component ( ), the electronic module having the control circuit ( ) and the programmable amplifier ( ); scanning the computer-readable indicia ( ); and providing the first data message to the control circuit ( ), wherein the first data message is based on the scanned computer-readable indicia ( ).

Circuit breaker having programmable amplifier

Auto chopping control during data acquisition for a circuit breaker

A feedback coder, which employs simple CMOS push/pull amplifiers as gain elements, along with a bistable circuit, in its preferred embodiment takes the form of a second-order delta-sigma modulator. The output of the modulator is converted into pulse code modulated words by a finite impluse response filter which incorporates a partial coefficient generator utilizing simplified logic. The generator output is provided to an accumulator in which the stage operate at reduced speed. A simple multiplexer generates a serial output. The entire converter can be integrated on a semiconductor chip of relatively small area.

Integrated analog-to-digital converter

A feedback coder, which employs simple CMOS push/pull amplifiers as gain elements, along with a bistable circuit, in its preferred embodiment takes the form of a second-order delta-sigma modulator. The output of the modulator is converted into pulse code modulated words by a finite impulse response filter which incorporates a partial coefficient generator utilizing simplified logic. The generator output is provided to an accumulator in which the stages operate at reduced speed. A simple multiplexer generates a serial output. The entire converter can be integrated on a semiconductor chip of relatively small area.

The input digital signal is applied to a transition detector which causes an up/down counter to increment or decrement each time a transition is detected. The output of the counter is utilized to address a read only memory (ROM) which, in turn, generates binary words representing first and second integers. These binary words are used to control a programmable divider to generate an output having a frequency which moves between two values corresponding to the digital input. The rate at which the frequency changes between the two values is controlled by the ROM contents. In the implementation, the frequency changes with a raised cosine shape.

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Kings Park, NY, United States of America

Peter Staley