Infineon Technologies Ag

Intel Mobile Communications Gmbh

Cree Gmbh

Peter Singerl

David Seebacher

Christian Schuberth

Martin Mataln

Andreas Wiesbauer

Thomas Magesacher

Herwig Wappis

Pantelis Sarais

Franz Dielacher

Ji Zhao

Thomas Blocher

Thomas Poetscher

Gernot Kubin

Christian Vogel

Andrea Del Chiaro

Heinz Koeppl

Dietmar Straeussnigg

Alexander Komposch

Haedong Jang

Thomas Ferianz

Richard Wilson

Marc Tiebout

Herbert Zojer

Gerhard Maderbacher

Wolfgang Horn

Thomas Pötscher

Johan Sjöström

Yannis Papananos

Nikolaos Alexiou

Tim Canning

Konstantinos Galanopoulos

Heinz Köppl

A circuit for biasing a transistor is provided. The circuit includes an output terminal configured to be coupled to a gate terminal of the transistor and circuitry. In a first state, the circuitry is configured to output a control signal at a first voltage level for setting the transistor to a first transistor state. In a second state, the circuitry is configured to first output the control signal at a second voltage level different from the first voltage level following by changing the control signal from the second voltage level towards a third voltage level different from the first and second voltage level over time.

Circuit and method for biasing a transistor and corresponding device

In sonic examples, a method includes pre-stressing a flange, heating the flange to a die-attach temperature, and attaching a die to the flange at the die-attach temperature using a die-attach material. In some examples, the flange includes a metal material, the die-attach temperature may be at least two hundred degrees Celsius, and the die-attach material may include solder and/or an adhesive. In some examples, the method includes cooling the semiconductor die and metal flange to a room temperature after attaching the semiconductor die to the metal flange at the die-attach temperature using a die-attach material.

Die-attach method to compensate for thermal expansion

Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.

Method and device for providing a bias voltage in transceivers operating in time division multiplexing operation

A device includes at least one electrically conductive structure and at least one stripline. The stripline includes stripline sections that are connected to one another in a series connection between a first terminal and a second terminal. A first subset of the stripline sections is arranged on a first side of the conductive structure and a second subset of the stripline sections is arranged on a second side of the conductive structure. The device also includes at least one conductive connection between the first subset of the stripline sections and the second subset of the stripline sections, wherein the at least one conductive connection is isolated from the at least one electrically conductive structure.

Device having at least one subset of stripline sections on opposite sides of an electrically conductive structure and configured to have positive coupling

A circuit includes a first power transistor stage internally configured to function as a voltage-controlled current source, a second power transistor stage having an input impedance which varies as a function of input power and an interstage matching network coupling an output of the first power transistor stage to an input of the second power transistor stage. The interstage matching network is configured to provide impedance inversion between the input of the second power transistor stage and the output of the first power transistor stage. The impedance inversion provided by the interstage matching network transforms the first power transistor stage from functioning as a voltage-controlled current source to functioning as a voltage-controlled voltage source at the input of the second power transistor stage.

Interstage matching network

Devices including a transistor having a parasitic capacitance between a control terminal and a load terminal of a first type are provided. Furthermore, the devices include advantageously arranged inductances which are electromagnetically coupled to one another and are configured at least partly to compensate for an effect of the parasitic capacitance in a range around a resonant frequency.

Compensation device for transistors

Method and device for providing a bias voltage in transceivers

Techniques are provided for sorting input data values using a sorting circuit. The sorting circuit includes a single stage of comparators coupled to a bank of registers. Multiplexors and a sequencer are used to route the comparator outputs back to the comparator inputs such that the comparators may be re-used over multiple sorting phases so as to order an input sequence of data values into a partially-sorted sequence or into a completely-sorted sequence that is monotonically increasing or decreasing. By re-using the comparators, the hardware required for such sorting is significantly reduced relative to conventional techniques. Also described are techniques for median filtering, which use a sorted sequence as output by the sorting circuit described herein.

Median filter that re-uses comparators when sorting data

An RF transmitter arrangement using analog pre-distortion is disclosed. The arrangement includes lower bandwidth circuitry, an analog pre-distorter, and a non-linear amplifier chain. The lower bandwidth circuitry is configured to generate an analog signal. The analog pre-distorter is configured to apply a non-linear distortion to the analog original signal based on a coupled feedback signal in order to generate an RF output signal. The non-linear amplifier chain is configured to amplify the RF output signal to generate a transmission signal relative to the analog original signal. The coupled feedback signal is derived from the transmission signal.

Analog RF pre-distorter and non-linear splitter

A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.

Devices and methods that facilitate power amplifier off state performance

A pulse width modulation system comprises an analog component and a digital component. The analog component operates to separate a local oscillator signal with different phase shifts and introduce an offset (i.e., a time delay) to analog signals being receive at an input with a tuning operation that fine tunes in the analog signals in the analog (continuous time) domain. The analog component comprises a plurality of analog delay lines that respectively process carrier signals having a different phase shifts. Digital delay lines convert the analog signals to digital square waves with the same time delay and at the same resolution as the analog output signal.

Mixed analog-digital pulse-width modulator

Techniques are provided for adapting a bias provided to a radio frequency (RF) power amplifier (PA), so as to achieve linear operation over a wide range of conditions. The techniques use open-loop temperature compensation based upon a sensed current during periods when the RF PA is active and inactive. A closed-loop control technique is enabled when the RF PA is inactive. The combined control techniques compensate for temperature variation as well as long-term drift of the semiconductor properties of the devices within the RF PA.

Adaptive biasing control for radio frequency power amplifiers

A non-linear pre-distortion engine maintaining constant peak power at its output is disclosed. The engine includes a compression estimator, a crest factor reduction processor, a digital pre-distorter and a power amplifier. The compression estimator is configured to generate a compression estimate based on an input signal and a feedback signal. The feedback signal is based on an RF output signal. The crest factor reduction processor is configured to reduce a crest factor of the input signal to generate a crest factor reduced signal based on the compression estimate. The digital pre-distorter is configured to apply a pre-distortion to the crest factor reduced signal after an initial phase and generate a pre-distorted signal based on pre-distortion parameters. The power amplifier is configured to amplify the pre-distorted signal to generate the RF output signal. The operation of the chain consisting of pre-distorter and power amplifier is substantially linear and the pre-distorter maintains constant peak power at its output, which eliminates unwanted avalanche or pre-distorter blow-up issues.

Devices and methods for adaptive crest factor reduction in dynamic predistortion

The present disclosure relates to a low-complexity transmitter architecture that drives phase modulators with digital signals to generate a pulse width modulated (PWM) signal that is transmitted by an antenna. In some embodiments, the system has a pre-processing element that generates first and second digital control signals from a digital baseband signal. A first phase modulation component introduces a first phase shift into a first local oscillator signal based upon the first control signal and generates a first digital signal corresponding to the first phase shift. A second phase modulation component introduces a second phase shift into the first local oscillator signal based upon the second control signal and generates a second digital signal corresponding to the second phase shift. A combination element is configured to combine the first and second digital output signals to generate an RF pulse width modulated (RF-PWM) signal.

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Villach, Austria

Peter Singerl