Hewlett-Packard Development Company, L.p.

Peter Shaw Moldauer

Mark D Frank

Jerimy Nelson

David W Quint

Jason Harold Culler

Gary Lewis Taylor

Karl Joseph Bois

Eric M Rentschler

William Bryson McHardy

Lisa Ann Yunker

A method for routing vias in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with an internal bond surface having a plurality of internal bond pads and an external bond surface with a plurality of external bond pads. A plurality of power vias and ground vias may be routed from a first redistribution layer between the internal bond surface and the external bond surface to a second redistribution layer between the first redistribution layer and the external bond surface based on a via pattern. The via pattern may comprise routing a power via and a ground via adjacent one another spaced apart at a distance that is substantially equal to a minimum routing pitch associated with the multilayer substrate.

Routing power and ground vias in a substrate

A multilayer substrate having a bonding surface is disclosed. One embodiment of the substrate may comprise a bypass capacitor connection pad disposed on the bonding surface. The bypass capacitor connection pad may have a bypass capacitor power pad and a bypass capacitor ground pad. The substrate may also comprise a plurality of power vias routed from the bypass capacitor power pad to a first redistribution layer spaced apart from the bonding surface and a plurality of ground vias routed from the bypass capacitor ground pad to the first redistribution layer. The substrate may further comprise a plurality of power and ground vias routed from the first redistribution layer to a second redistribution layer according to a power and ground via pattern array, wherein the plurality of ground vias are jogged at the first redistribution layer to the plurality of power vias to form the power and ground via pattern array.

Routing vias in a substrate from bypass capacitor pads

A method and structure for external control of an electrostatic discharge (ESD) protection of electronic devices. According to the structure, one or more shunt circuits are coupled to the electronic devices and one or more external contacts are coupled to the one or more shunt circuits. One or more power supplies are further coupled to the one or more shunt circuits prior to the shunt circuits being coupled to the electronic devices. According to the method, the one or more external contacts are operable to be used to perform on or more of: grounding one or more of one or more external contacts coupled to the one or more shunt circuits, supplying one or more DC signals to one or more of the one or more shunt circuits via one or more of the one or more external contacts, and supplying one or more AC signals to one or more of the one or more shunt circuits via one or more of the one or more external contacts.

Method and structure for external control of ESD protection in electronic circuits

A method for routing signals in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with at least one differential signal line pair aligned along a common plane that is substantially transverse to a top surface of the multilayer substrate, jogging a first differential signal line associated with a differential signal line pair at a first redistribution layer in a direction along the common plane, and jogging a second differential signal line associated with the differential signal line pair at a second redistribution layer along the common plane in a same direction as the first differential signal line to provide a substantially balanced differential signal line pair.

Routing differential signal lines in a substrate

A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.

Techniques are disclosed for verifying the proximity of ground vias to signal vias in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a ground via within a predetermined threshold distance of each specified signal via in the package design. The proximity verifier may notify the package designer of any signal vias which are not sufficiently close to ground vias, such as by providing visual indications of such signal vias in a graphical representation of the package design displayed on a display monitor. In response, the package designer may modify the package model to ensure that all signal vias are sufficiently close to ground vias. The proximity verifier may be implemented as a design rule which may be executed automatically and in real-time by the package design tool.

Verifying proximity of ground vias to signal vias in an integrated circuit

A method and apparatus for modifying a frequency of an oscillating signal comprises generating an oscillating signal of a predetermined frequency on a semiconductor device used as an evaluation test chip by connecting a predetermine number of circuit elements in a ring oscillator configuration. A delay element operably coupled into the ring oscillator configuration modifies the predetermined frequency of the ring oscillator configuration. The operable coupling may occur on a semiconductor package containing the semiconductor device or a circuit board containing the semiconductor device. A ring oscillator is also described.

Oscillator method and apparatus for a test chip

In one aspect, techniques are disclosed for identifying and notifying a circuit designer of signal traces in an integrated circuit design that are closer to each other than a proximity threshold. It is desirable that signal traces be separated from each other by at least the proximity threshold to reduce inter-signal crosstalk to an acceptable level. Such notification may occur either dynamically (while the circuit designer is designing the circuit) or through a report generated after the circuit design has been generated. In another aspect, techniques are disclosed for identifying and notifying the circuit designer of the signal traces that are closest to a reference signal trace. Such notification may provide the circuit designer with feedback about regions in the circuit design which are congested and which may therefore produce an unacceptable level of crosstalk.

Inter-signal proximity verification in an integrated circuit

A signal pathway is presented for routing clock signals from a clock driving device to a circuit component and on to a termination. The signal pathway employs a minimal stub to carry the clock signals to the circuit component without introducing excess signal distortions. A first signal line of the signal pathway is formed on a circuit board and extends from the clock driving device to a first terminal for interfacing with the circuit component. A second signal line of the signal pathway is routed on the circuit component from one end adjacent to and electrically coupled with the first terminal to an opposite end adjacent to and electrically coupled with a second terminal formed on the circuit board. The stub extends from the second signal line on the circuit component. A third signal line of the signal pathway extends on the circuit board from the second terminal to the termination.

Terminating pathway for a clock signal

Techniques are disclosed for verifying the proximity of signal return paths (e.g., ground metal or power) to signal traces in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a signal return path within a predetermined threshold distance of each specified signal trace in the package layers directly above and/or below the signal trace. The proximity verifier may notify the package designer of any signal traces which are not sufficiently close to signal return paths, such as by providing visual indications of such signal traces in a graphical representation of the package design. In response, the package designer may modify the package model to ensure that all signal traces are sufficiently close to signal return paths.

Verifying proximity of ground metal to signal traces in an integrated circuit

Techniques are disclosed for automatically synthesizing information from a plurality of computer-readable integrated circuit package models. In one embodiment, each of the plurality of package models contains information descriptive of a distinct package. Such information may include, for example, intra-package path lengths and/or propagation delays of signal nets in the modeled packages. Techniques are disclosed for automatically synthesizing such information to produce, for example, aggregate path lengths and/or propagation delays of the signal nets across all of the modeled packages. Such synthesis may be performed even when the package models use mutually inconsistent signal net naming conventions and the modeled packages are composed of different materials. Techniques are also disclosed for providing information to the package designer to assist the package designer in improving the design of the package models.

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Wellington, CO, United States of America

Peter Shaw Moldauer