Micron Technology Incorporated

Peter Sean Feeley

Kishore Kumar Muchherla

Sampath K Ratnam

Ashutosh Malshe

William Henry Radke

Sivagnanam Parthasarathy

Mustafa Nazmi Kaynak

Shane G Nowell

Victor Y Tsai

Neal Anthony Galbo

Harish Reddy Singidi

Koji Sakui

Renato C Padilla

Vamsi Pavan Rayaprolu

Michael G Miller

Robert N Leibowitz

Christopher S Hale

Aswin Thiruvengadam

Gary F Besinga

Yun Li

Daniel L Lowrance

Zhenlei Shen

Kevin Roy Brandt

Daniel J Hubbard

Jiangang Wu

Xiangang Luo

Devin M Batutis

Karl David Schuh

Preston Allen Thomson

James Cooke

Jung Sheng Hoei

Kulachet Tanpairoj

Renato Padilla, Jr

Qisong Lin

Violante Moschiano

Theodore T Pekny

Gianni Stephen Alsasua

Akira Goda

Bruce A Liikanen

Jianmin Huang

Larry Joseph Koudele

Michael Sheperek

Ting Luo

Steven Michael Kientz

Marc S Hamilton

Jiangli Zhu

Siamack Nemazie

Fangfang Zhu

Sanjay Subbarao

Dave Scott Ebsen

Walter Di-Francesco

Lakshmi Kalpana Vakati

Vivek Shivhare

Scott Anthony Stoller

Cory M Steinmetz

Mark Alan Helm

Chad A Cobbley

Lance W Dover

Koichi Kawai

Wanmo Wong

Brady L Keays

Giuseppina Puzzilli

Saeed Sharifi Tehrani

Yifen Liu

Sead Zildzic

Pushpa Seetamraju

Samuel A Shapero

Jim Cooke

Tomoko Ogura Iwasaki

Michael M Abraham

Robert N Liebowitz

Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.

Multiple-pass programming of memory cells using temporary parity generation

A method includes identifying, by a processing device, a common pool of blocks comprising a first plurality of blocks allocated to system data and a second plurality of blocks allocated to user data; determining whether user data has been written to the second plurality of blocks within a threshold period of time; and responsive to determining that the user data has not been written to the second plurality of blocks within the threshold period of time, allocating a block from the second plurality of blocks to the first plurality of blocks.

Using a common pool of blocks for user data and a system data structure

An amount of voltage shift is determined for one or more memory cells of a block family based on an initial reference value pertaining to the one or more memory cells and a subsequent reference value pertaining to the one or more memory cells. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

Voltage bin calibration based on a voltage distribution reference voltage

The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.

Trim setting determination for a memory device

An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.

Block family-based error avoidance for memory devices

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.

Managing error-handling flows in memory devices

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Memory device with dynamic cache management

Memory devices are disclosed. A memory device may include dynamic cache, static cache, and a memory controller. The memory controller may be configured to disable the static cache responsive to a number of program/erase (PE) cycles consumed by the static cache being greater than an endurance of the static cache. The memory controller may also be configured to disable the dynamic cache responsive to a number of PE cycles consumed by the dynamic cache being greater than an endurance of the dynamic cache. Associated methods and systems are also disclosed.

Memory devices and systems including static and dynamic caches, and related methods

Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.

Buffer allocation for reducing block transit penalty

A method includes initiating a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin, measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin, determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets, and in response to determining that the value is less than the current value, designating the second bin as the current bin.

Voltage calibration scans to reduce memory device overhead

Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.

Memory block programming using defectivity information

A current value for a reference voltage for a block family is determined. An amount of voltage shift for a memory page of the block family is determined based on the current value for the reference voltage and a prior value for the reference voltage. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; identify, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block; identify, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.

Managing voltage bin selection for blocks of a memory device

An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

Implementing fault tolerant page stripes on low density memory systems

Growing community of inventors

Boise, ID, United States of America

Peter Sean Feeley