Infineon Technologies Ag

Siemens Aktiengesellschaft

Infineon Technology Ag

Peter Schr&ouml;gmeier

Stefan Dietrich

Christian Weis

Sabine Sch&ouml;niger

Thomas Hein

Torsten Partsch

Thilo Marx

Patrick Heyne

Sabine Kieser

Michael Markert

Michael Bernhard Sommer

Pramod Acharya

Musa Saglam

Sabine Sch&ouml;niger Kieser

Latency time circuit for an S-DRAM ( ), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path ( ) of the S-DRAM ( ), having a controllable latency time generator ( ) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which a comparison circuit ( ) which compares a cycle time (t ) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path ( ), and reduces the latency time of the latency time generator ( ) by the cycle time if the signal delay time of the data path ( ) is greater than the cycle time (t ) of the clock signal (CLK)

Latency time switch for an S-DRAM

The circuit configuration has a memory array, a memory access controller, a control unit, and an input/output circuit. The control unit outputs a control signal simultaneously to the memory access controller and to the input/output circuit. When the control signal is received, the input/output circuit outputs data to the memory access controller via the data bus. When the control signal is received, the memory access controller stores the data present on the data bus in memory cells of the memory array. Owing to different geometric arrangements and different electrical capacitances, differences in propagation time of the control signals may occur on the path from the control unit to the memory access controller and from the control unit to the input/output circuit. For this purpose, a delay circuit or delay line is provided on the signal path to the memory access controller which brings about a delay of the control signal. This enables precise synchronization of the writing of data into the memory array.

Circuit configuration with a memory array

The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a terminal for feeding in a supply voltage and the terminal for tapping off the boosted output voltage. After the voltage pump has started to operate, the boosted output voltage is decoupled from the supply voltage by the transistor. A changeover switch forwards the respective higher of the output voltage or supply voltage to the substrate terminal and gate terminal of the transistor. The switch-on control enables early provision of a boosted output voltage in conjunction with reliable start-up operation of the voltage pump, while the additional outlay on circuitry is minimized.

Voltage pump with switch-on control

A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.

Circuit configuration for programming a delay in a signal path

The integrated memory has a first address path, via which the address terminals are connected to first selection lines of a first group and which has corresponding first lines and a first decoder circuit. In addition, the integrated memory has a second address path, via which the address terminals are connected to first selection lines of a second group and which has corresponding second lines and a second decoder circuit. The first decoder circuit is faster than the second decoder circuit. The first lines have a longer signal propagation time than the second lines.

Integrated memory

The integrated circuit has an activation decoder whose outputs are connected to the inputs of a command decoder. When an activation signal is at a first logic level, the activation decoder produces at its outputs a command supplied to it from command inputs. When the activation signal is at a second logic level, the activation decoder produces a deactivation command at its outputs irrespective of the command supplied to it from the command inputs. The command decoder does not activate any of its outputs when the deactivation command is being supplied to its inputs. The command decoder activates one of its outputs in each case when a different command is supplied to its inputs.

Integrated circuit having a command decoder

A test method suitable for testing at least one integrated circuit which, on a main area, has contact areas that serve to transfer signals during a first operating mode of the circuit. Only some of the contact areas are contact-connected to test contacts of a test apparatus and the circuit is put into a second operating mode in which the signals which are transferred via at least one of the non-contact-connected contact areas in the first operating mode are transferred via at least one of the contact-connected contact areas.

Integrated circuit and method for testing it

An integrated memory has memory cells which are each connected to a row line to select one of the memory cells and to a column line to read or write a data signal. A row access controller is used to activate one of the row lines to select one of the memory cells and to control a precharging operation to precharge one of the row lines. A precharge command initiates a precharging operation. The precharging operation for an activated row line is triggered by the row access controller when the reading or writing of a data signal has been finished and when a defined time interval, during which the row line must at least be activated, has elapsed since the activation. As a result, a precharging operation of the activated row line is controlled in a self-adjusting manner. A method of operating an integrated memory is also provided.

Integrated memory with row access control to activate and precharge row lines, and method of operating such a memory

A memory chip with a short data access time limits the propagation time of a bit on local data line strips which are far away from output amplifiers by centering switches with respect to a center of the cell array strips, wherein the switches are junction points between local data lines and main data lines.

Memory component with short access time

The integrated circuit has a first decoder unit and a second decoder unit D connected in parallel with the latter, which decode the input signals fed to them in a different way in each case. The inputs of the second decoder unit D are connected to a respective one of the inputs of the first decoder unit D n lines L to be selected are each connected to a respective one of the outputs of the two decoder units D D Via their outputs, the first decoder unit D and the second decoder unit D determine, in a first operating mode and in a second operating mode, respectively, the potentials of the lines L to be selected.

Integrated circuit having a decoder unit and an additional input of a decoder unit to determine a number of outputs to be activated

A read-write mode control method is described in which a waiting time during a reading process can be shortened by conducting a read instruction with auto-precharging in a first circuit part. The first circuit part is separate from a second circuit part used for conducting the write instruction, since a memory controller does not need to insert any wait cycles between a write instruction and an associated activate signal.

Method and circuit configuration for read-write mode control of a synchronous memory

An integrated memory has a first operating mode, in which, during each write access, only one of the two global amplifiers is active and transmits a datum via one of the local amplifiers to the corresponding bit line. Moreover, the memory has a second operating mode, in which, during each write access, both global amplifiers are simultaneously active and transmit a common datum via in each case at least one of the local amplifiers to the corresponding bit lines.

Integrated memory with a block writing function and global amplifiers requiring less space

The memory has a bidirectional address counting unit C,S, which performs a counting operation for the purpose of generating internal column addresses from an external column address A,In this case, the counting direction is dependent on the burst operating mode and on an address bit A,of the external column address. Moreover, the memory has a transformation unit C,SR,which forwards partial addresses A,&prime;; PA,&prime; generated by the address counting unit C,S either unchanged or incremented by the value,to the second column decoder CDEC,in a manner dependent on the burst operating mode and a further address bit A,of the external column address A

Integrated memory with two burst operation types

Each redundant unit of an integrated memory device is assigned respective programmable elements, comparison units, a code converting unit, a logic unit and a multiplexer. Each multiplexer has a first switching state, in which it connects outputs of the first comparison units to first inputs of the logic unit, and a second switching state, in which it connects outputs of the code converting unit to the first inputs of the logic unit. In the second switching state of the multiplexers, each redundant unit is assigned a different address in the unprogrammed state of the programmable elements. Therefore, redundant units can be selected individually for test purposes.

Integrated memory having redundant units of memory cells, and test method for the redundant units

A memory has data lines through which data connections are connected to groups of memory cells via a synchronizing unit. The synchronizing unit is disposed adjacent to the cell group and has a clock input to which an internal clock signal is fed. In the event of a write access to the memory, the synchronizing unit synchronizes with the internal clock signal data signals that are fed via the data connections and are synchronous with an external clock signal.

Growing community of inventors

München, Germany

Peter Schrögmeier

Growing community of inventors

München, Germany

Peter Schr&ouml;gmeier

Peter Schrögmeier