Infineon Technologies Ag

Peter Scherl

Frank Pueschner

Juergen Hoegerl

Alexander Heinrich

Christian Neugirg

Thorsten Meyer

Horst Theuss

Gerald Ofner

Stephan Bradl

Stefan Miethaner

Adrian Lis

Andreas Karl

Andreas Mueller-Hipper

Magdalena Hoier

Matthias Gruenauer

Ivan Nikitin

Manfred Schneegans

Hans-Joerg Timme

Irmgard Escher-Poeppel

Peter Stampka

Raimund Foerg

Thomas Kunstmann

Eduard Knauer

Achim Althaus

Roman Hollweck

Ewald Guenther

Kristof Bothe

Uwe Wagner

Described are solder stop features for electronic devices. An electronic device may include an electrically insulative substrate, a metallization on the electrically insulative substrate, a metal structure attached to a first main surface of the metallization via a solder joint, and a concavity formed in a sidewall of the metallization. The concavity is adjacent at least part of the solder joint and forms a solder stop. A first section of the metal structure is spaced apart from both the metallization and solder joint in a vertical direction that is perpendicular to the first main surface of the metallization. A linear dimension of the concavity in a horizontal direction that is coplanar with the metallization is at least twice the distance by which the first section of the metal structure is spaced apart from the first main surface of the metallization in the vertical direction. Additional solder stop embodiments are described.

Solder stop feature for electronic devices

A semiconductor package includes: a first substrate having a first metallized side; a semiconductor die attached to the first metallized side of the first substrate at a first side of the die, a second side of the die opposite the first side being covered by a passivation, the passivation having a first opening that exposes at least part of a first pad at the second side of the die; a thermally and electrically conductive spacer attached to the part of the first pad that is exposed by the first opening in the passivation, the spacer at least partly overhanging the passivation along at least one side face of the semiconductor die; a second substrate having a first metallized side attached to the spacer at an opposite side of the spacer as the semiconductor die; and an encapsulant encapsulating the semiconductor die and the spacer. Additional spacer embodiments are described.

Semiconductor package having a thermally and electrically conductive spacer

A semiconductor package includes a first power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the first power electronics carrier, and a first pair of metal pads that are immediately laterally adjacent one another and are low-voltage difference nodes of the semiconductor package, a second pair of metal pads that are immediately laterally adjacent one another and are high-voltage difference nodes of the semiconductor package, and an encapsulant body of electrically insulating material that encapsulates the power semiconductor die and the first and second pairs of metal pads, wherein the first pair of the metal pads are laterally isolated from one another by a first minimum separation distance, and wherein the second pair of the metal pads are laterally isolated from one another by a second minimum separation distance that is greater than the first minimum separation distance.

Semiconductor package with power electronics carrier having trench spacing adapted for delamination

A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.

Flat lead package formation method

A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.

Semiconductor chip package comprising substrate, semiconductor chip, and leadframe and a method for fabricating the same

A method of producing packaged semiconductor devices includes providing a first packaging substrate panel, providing a second packaging substrate panel, and moving the first and second packaging substrate panels through an assembly line that comprises a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner. The first and second packaged semiconductor devices differ with respect to at least one of: lead configuration, and encapsulant configuration.

Multi-purpose non-linear semiconductor package assembly line

A semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate. An important aspect in development of the semiconductor chip package is improvement of connections between different components within the package.

Semiconductor chip package comprising a leadframe connected to a substrate and a semiconductor chip, and a method for fabricating the same

A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The first and second packaging substrate panels are moved through an assembly line that includes a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The second type packaged semiconductor device is different than the first type packaged semiconductor device. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner.

Various embodiments provide a method of forming a bondpad, wherein the method comprises providing a raw bondpad, and forming a recess structure at a contact surface of the raw bondpad, wherein the recess structure comprises sidewalls being inclined with respect to the contact surface.

Method of forming a bondpad and bondpad

An electronic device may comprise a semiconductor element and a wire bond connecting the semiconductor element to a substrate. Using a woven bonding wire may improve the mechanical and electrical properties of the wire bond. Furthermore, there may be a cost benefit. Woven bonding wires may be used in any electronic device, for example in power devices or integrated logic devices.

Electronic device and method of fabricating an electronic device

In various embodiments, a smart card module arrangement is provided. The smart card module arrangement includes a carrier, in which a depression is formed, a smart card module, which is arranged in the depression, and a smart card antenna. The smart card antenna can be coupled to the smart card module in a contactless manner.

Smart card module arrangement

An embodiment method for fabricating electronic devices having two components connected by a metal layer includes applying a metal layer to each component and connecting the metal layers such that a single metal layer is formed.

Electronic device and method for fabricating an electronic device

In various embodiments a chip arrangement is provided, wherein the chip arrangement may include a chip and at least one foil attached to at least one side of the chip.

Chip arrangement and a method for manufacturing a chip arrangement

A smart card module for a smart card, comprising a chip having electrical contacts at a front side; a first laminate layer, wherein a rear side of the chip is connected to the first laminate layer, the rear side of the chip opposite the front side; a second laminate layer; a first conductive layer, wherein the electrical contacts of the chip are connected to the first conductive layer and the first conductive layer is arranged between the chip and the second laminate layer; and an adhesive material arranged between the chip and the conductive layer and/or the second laminate layer.

Smart card module for a smart card

In various embodiments, a cover structure for a personal identification document is provided. The cover structure may include a cover formed as a single layer; a chip module; the cover having a recess for completely receiving the chip module; and an antenna that is connected to the chip module.

Growing community of inventors

Wuppertal, Germany

Peter Scherl