Texas Instruments Corporation

Peter S Ying

Louis N Hutter

Imran Khan

Marco Corsi

Clarence W Teng

Ming J Hwang

Jing Shing Shu

Toyotaro Horiuchi

Capacitors for integrated circuits with a common polysilicon layer for both MOS gates ( ) and capacitor ( ) lower plates but with implanted doping for the gates and masked diffusive doping for the capacitor plates.

Integrated circuit capacitor and method

A method for fabricating a BiCMOS integrated circuit. The method includes the steps of forming in a single implantation step a base region of a bipolar transistor and a p-well of an n-channel MOS transistor; and forming in a single implantation step a collector contact well of a bipolar transistor and an n-well of a p-channel MOS transistor.

Merged bipolar and CMOS circuit and method

This is a system and method of in-situ coating, baking and curing of dielectric material. The system may include: dispensing apparatus for dispensing spin-on material; a lamp module 50; a window 54 connected to the lamp module 50; an environmental control chamber 56 connected to the window 54; an access gate 60 for wafers 58 in the environmental control chamber 56; a spin chuck 62 inside the environmental control chamber 56; and an exhaust pipe 64 connected to the environmental control chamber 56. The lamp module 50 may contains infra red and ultra violet lamps. In addition, the coating chamber may process dielectric material such as spin-on glass, silicon dioxide and various other spin-on material.

In-situ coat, bake and cure of dielectric material processing system for

A method for forming a planar insulating layer over the surface of a semiconductor workpiece 8 which includes at least one low region 13 is discussed herein. The first step is to form a layer of blocking material 14 on the surface of the workpiece 8. A first material region 20 is then formed in the low region 13 and an insulating layer 21 is formed over the surface of the workpiece 8 including the first material region 20. The workpiece 8 is then heated in the presence of an active ambient such that the insulation layer 21 reflows and also so that the first material 20 region reacts with the active ambient to create an internal stress in said insulation layer 21. Other systems and methods are also disclosed.

Method of forming a planarized insulation layer

The described embodiments of the present invention provide DRAM cells, structures and manufacturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. In another embodiment of the present invention, a planar capacitor is used with a field plate isolation scheme including a transfer transistor moat region self-aligned to the field plate. This structure allows the elimination of alignment tolerances between the capacitor and the transistor thus reducing the space necessary between the transistor and the capacitor. In another embodiment of the present invention, a memory cell using two conductive plates formed inside a trench as the storage capacitor is fabricated. A field plate isolation scheme which allows for self-alignment of the moat containing the transfer transistor is used thus allowing for self-alignment of the moat and elimination of alignment tolerances between the moat region and the source drain diffusions. In addition, a sidewall insulator technique using two different materials, which may be selectively etched between one another, is used.

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Plano, TX, United States of America

Peter S Ying