Texas Instruments Corporation

Peter S McAnally

Jeffrey A McKee

Kenneth D Brennan

David Brian Aldrich

Eden M Zielinski

Theodore Warren Houston

Amitava Chatterjee

Frank Scott Johnson

Somnath S Nag

Keith Alan Joyner

Dirk N Anderson

Darius Lammont Crenshaw

Ih-Chin Chen

Siang Ping Kwok

Yin Hu

Iqbal Ali

Agerico L Esquirel

A structure and method to direct the via,etch to the top of the interconnect,by using a sidewall layer,preferably. TiN, and thus preventing the etching down the side of the interconnect,and exposure of materials residing between the interconnects

Sidewalls for guiding the via etch

A self-aligned contact (122) to a substrate (12) of a semiconductor device (100) is formed using a stopping layer (110) overlying the substrate (12). The stopping layer (110) comprising a material selected from the group consisting of silicon-rich nitride, silicon-rich oxide, carbon-rich nitride, silicon carbide, boron nitride, organic spin-on-glass, graphite, diamond, carbon-rich oxide, nitrided oxide, and organic polymer. The stopping layer (110) promotes better semiconductor device (100) performance by contributing to greater selectivity with respect to an etch process used to remove an insulating layer (112) formed overlying the stopping layer (110).

Method for enhancing the performance of a contact

A method for fabricating a spacer in a transistor. The method comprises the steps of forming a stepped feature 384, 386 at a surface of a semiconductor body 340, the stepped feature having a lateral face substantially parallel to the surface and an angled face substantially perpendicular to the surface. An insulating layer 410 is formed over the lateral and angled faces of the stepped feature 384, 386 and a sacrificial layer 404 is formed over the insulating layer and over the lateral and angled faces of the stepped feature. The portion of the sacrificial layer over the lateral face is removed to expose portions of the insulating layer and to leave a portion of the sacrificial layer to cover the angled face of the stepped feature. Finally, the exposed portions of the insulating layer are removed to leave an L-shaped insulator layer, such as may be useful to insulate the base electrode from the emitter electrode in a bipolar transistor.

Bipolar transistor with L-shaped base-emitter spacer

A structure and method to direct the via 270 etch to the top of the interconnect 210, by using a sidewall layer 240, preferably TiN, and thus preventing the etching down the side of the interconnect 210 and exposure of materials residing between the interconnects 210.

A contact (26) to a substrate (12) is formed using a first stopping layer (14), an insulating layer (16), and a second stopping layer (18). The second stopping layer (18) promotes a more accurate and controlled removal of the first stopping layer (14). A self-aligned contact (122) may be formed in a similar manner using a first stopping layer (110), an insulating layer (112), and a second stopping layer (114).

Method for forming a contact to a substrate

A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to 'dishing' that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.

Reducing non-uniformity in a refill layer thickness for a semiconductor

A planarized capacitor array (182) and method of forming the same for high density applications. A storage node contact (116) is formed through an interlevel dielectric (110) on a semiconductor body (102). Then, an oxide layer (170) having a first thickness is deposited over the interlevel dielectric (110) and the storage node contact (116). A nitride layer (172) having a second thickness is deposited over the oxide layer (170) to protect the oxide layer (170) during later processing. The nitride layer (172) and oxide layer (170) are then patterned and etched to form a storage plate cavity (180). The capacitor array (182) is then formed in the storage plate cavity (180). The capacitor array (182) has a height approximately equal to the sum of said first and second thicknesses, so that the surface of the top node of the capacitor array (182) is co-planar with the upper surface of the surrounding oxide/nitride stack (170/172). Thus, the step height normally present between the capacitor array (182) and the peripheral area is avoided.

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McKinney, TX, United States of America

Peter S McAnally