Advanced Micro Devices Corporation

Peter S Gwozdz

Christopher O Schmidt

William L Price

Bert L Allen

Hubert M Bath

Thomas R Bowers

A method is described for producing an integrated circuit structure, including EPROMS, having excellent resistance to penetration by moisture and ion contaminants and a substantial absence of voids in an underlying metal layer in the structure, and, in the case of EPROMS, maintaining sufficient UV light transmissity to permit erasure which comprises stress relieving the underlying metal layer from stresses induced by the compressive stress of a silicon nitride encapsulating layer to inhibit the formation of voids therein by implanting the metal layer with ions to change the grain structure adjacent the surface of the metal layer; forming an insulating intermediate layer between said the layer and the silicon nitride layer selected from the class consisting of an oxide of silicon and silicon oxynitride having a compressive/tensile stress which sufficiently compensates for the compressive stress of the silicon nitride layer; and controlling the compressive stress in the silicon nitride layer to provide resistance to moisture and ion penetration superior to silicon dioxide or silicon oxynitride layers of similar thickness while inhibiting formation of voids in the metal layer.

Passivation for integrated circuit structures

A process is disclosed for filling a trench in an integrated circuit structure without forming a void in the trench which, in a preferred embodiment, comprises partially filling the trench with an etchable material, etching the material in the trench with an etchant capable of removing material adjacent the top of the trench at a rate faster than the rate of removal adjacent the bottom of the trench, and then filling the remainder of the trench with the material; whereby the material deposited adjacent the top of the trench will not close off the trench prior to complete filling of the bottom of the trench with the material.

Method for filling a trench in an integrated circuit structure without

A method is presented for fabricating a bipolar semiconductor device utilizing a combination of junction isolation, oxide isolation, stepper lithography and plasma etching to produce an integrated circuit device having reduced device sizes and increased performance. The method includes the steps of removing portions of a masking layer to expose surface areas of an epitaxial layer, where first type isolation regions are then formed; then forming second type isolation regions in the epitaxial layer, and forming base, emitter and collector contact regions, also in the epitaxial layer; and forming conductive lines on the base, emitter and collector contact regions.

Method of making integrated bipolar semiconductor device by first

An improved method for forming a conductive path through at least one layer of insulating material in an integrated circuit structure comprising a narrow portion and a sloped oversized portion of the conductive path. The method comprises forming the sloped oversize portion of the conductive path by defining an opening in a layer of photoresist material applied over the layer of insulating material, sloping the edges of the photoresist layer adjacent the opening to define an angle with the plane of the underlying insulating layer, and etching the photoresist layer and the insulating layer with an etchant capable of removing both materials to form the sloped oversized portion of the conductive path. The narrow portion of the conductive path is formed by etching at least a portion of the insulating layer to expose a selected section of the integrated circuit structure below the insulating layer. Either the oversized sloped portion or the narrow portion may be formed first. Planarization can be carried out prior to formation of the conductive path and/or during formation of the oversized sloped portion.

Method for interconnecting conducting layers of an integrated circuit

A method for forming multiple conductive interconnect layers on a semiconductor device comprises defining a first conductive metal layer, applying a first insulating layer thereon, planarizing the first insulating layer by etching a sacrificial planarization layer, applying a second insulating layer, forming vias through first and second insulating layers and applying a second conductive layer thereon. Optionally, a third insulating layer can be applied over the first two and stepped vias formed to improve the interconnection of the first and second layers. The method reduces metallization failure associated with irregularities in the intermediate insulating layers.

Growing community of inventors

Cupertino, CA, United States of America

Peter S Gwozdz