Gte Communication Systems Corporation

Peter S Bernardson

Pivot board exercise device

A modulo 2.sup.2n -1 adder employing adders which may all be standard binary adders. A first binary adder sums binary input signals a and b to produce a first sum signal in which the n+2 more significant bits represent the integer part of (a+b)/2.sup.2n (i.e., of a+b taken modulo 2.sup.2n). A second binary adder subtracts these n+2 more significant bits from a 2n bit shifted (less significant bits) version thereof for producing a first difference signal which is subtracted from the first sum signal in a third binary adder to produce a binary signal R. The signal R is applied to one input of a fourth binary adder which produces the desired modulo 2.sup.2n -1 signal. A comparator circuit applies a constant (2.sup.2n -1) to a difference input of the fourth binary adder only when R is greater than or equal to this constant.

Modulo adder

A residue to analog converter associated with residue numbers {m1,m2,m3} of the residue number system defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1} and which does not require memory comprises five standard binary adder circuits, apparatus for performing multiplication by bit shifting, and a modulo p1 p3 adder circuit. First and second binary adders combine the residue signals m1 and m3 to produce sum and difference signals which are bit shifted by grounding 2n-1 and n-1 lines, respectively, and locating them as less significant bit lines ahead of these sum and difference signal lines. A modulo p1*p3 adder sums these bit shifted signals. A third binary adder, which ignores overflow, performs a modulo p2=2.sup.n subtraction of m2 from the n less significant bits of the modulo p1*p3 sum signal to produce a second difference signal. This second difference signal is bit shifted by 2n grounded lines that are connected as less significant bit lines ahead of this signal, and then subtracted from this bit shifted signal in a fourth binary adder to produce a correction signal. The modulo p1*p3 sum signal and the correction signal are summed in a fifth binary adder to produce a three dimensional binary signal r(m1,m2,m3) that is representative of a residue signal {m1,m2,m3}. The corresponding analog signal is produced with a standard D/A converter. Structure for implementing the modulo p1*p3 adder circuit with adders that are all standard binary adders is disclosed.

Residue to analog converter

In a residue number system defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1}, a method of converting residue numbers {m1,m2,m3} to associated analog signals r(m1,m2,m3) comprises the steps of selecting a first binary signal satisfying the relationships .vertline.m1*S3+m3*S1.vertline..sub.p1*p3 (where the constant S1=p1*p2/2 and S3=p2*p3/2) from a first look-up table; and summing the n less significant bits of this first digital signal and the negative of the residue digit signal m2 in a first binary adder for generating a second binary signal that is representative of the difference therebetween, taken modulo p2. This second binary signal addresses a second look-up table containing third binary signals which correspond to possible values of the product of the second binary signal and p1 and p3. Selected first and third binary signals are summed in a second binary adder for producing a binary output signal r(m1,m2,m3) that is representative of the residue number {m1,m2,m3}. This binary output signal is converted to a corresponding analog signal in a standard D/A converter. In an alternate method, 2n binary 0's are stuffed as less significant bits of the second binary signal prior to subtracting the latter from this bit shifted signal for producing the third binary signal. In yet another method, the first binary signal is obtained by selecting the binary signals m1*S3 and m3*S1 from associated look-up tables prior to summing them modulo p1*p3.

Method of residue to analog conversion

A method is disclosed for accomplishing modulo 2.sup.2n -1 addition with apparatus requiring adders that may be all standard binary adders. The method requires summing binary input signals a and b to produce a first sum signal in which the n+2 more significant bits thereof represent the integer part of a+b taken modulo 2.sup.2n. These n+2 more significant binary bits are subtracted from a 2n bit shifted product representation thereof for producing a first difference signal. This difference signal is subtracted from the first sum signal to produce a binary signal R. When R is greater than or equal to the constant (2.sup.2n -1), this constant is subtracted from the signal R for producing a binary signal that is the first sum signal a+b taken modulo 2.sup.2n -1 .

In a residue number system defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1}, a method of converting residue number signals {m1,m2,m3} to associated analog signals r(m1,m2,m3), and that does not require memory devices, comprises the steps of generating a pair of binary signals that are the sum and difference of the residue numbers m1 and m3, bit shifting these sum and difference signals by inserting 2n-1 and n-1 binary 0's as less significant bits thereof, and summing these bit shifted signals modulo p1*p3 to produce a two dimensional binary signal r(m1,m3). A correction signal is generated by modulo p2=2.sup.n summing the n less significant bits of the signal r(m1,m3 ) and the negative of the residue signal m2 to produce a second difference signal, bit shifting this second difference signal by inserting 2n binary 0's as less significant bits thereof and subtracting the second difference signal from this bit shifted signal to produce the correction signal. The signal r(m1,m3) and the correction signal are summed for producing a binary representation r(m1,m2,m3) of a given residue number {m1,m2,m3} . This binary signal is converted to the corresponding analog signal in a standard D/A converter. In a preferred embodiment, apparatus for performing the modulo p1*p3 summation is implemented with combining circuits that may be all standard binary adders so that all of the combining is done with standard binary adders and that no memory devices are required to perform the desired residue to binary conversion.

A residue to analog converter associated with residue numbers {m1,m2,m3} of the RNS defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1} comprises a pair of ROMs and a pair of standard binary adders. The first ROM stores a look-up table of summations, taken modulo p1*p2, of possible values of m1*S3 and m3*S1 product terms, where S1=(p1*p2)/2 and S3=(p2*p3)/2, with associated memory locations being addressed by m1 and m3. The first binary adder performs a modulo 2.sup.n summation of a binary signal stored by the first ROM and -m2 by ignoring any overflow. The second ROM stores a look-up table of possible values of the products of p1, p3 and the modulo 2.sup.n signal. The second binary adder sums output signals of the two ROMs for producing a binary signal r(m1,m2,m3) that is representative of the residue signal {m1,m2,m3}. The corresponding analog signal is produced with a standard D/A converter. In an alternate embodiment, look-up tables of possible m1*S3 and m3*S1 product terms are stored in associated ROMs and summed in a modulo p1*p3 adder. In yet another embodiment, the second ROM is replaced with means for bit shifting the modulo p2=2.sup.n signal prior to subtracting the latter from the bit shifted signal in a standard binary adder which takes overflow into consideration.

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Tempe, AZ, United States of America

Peter S Bernardson