International Business Machines Corporation

Peter Rudolph

Hans H Lampe

Jeffrey Joseph Ruedinger

Dietmar Schmunkamp

Dietrich W Bock

Werner H Pohle

Halim S Tandjung

Guenter Hahn

Heinz Drescher

Peter Mannherz

Hermann Schulze Scholling

Stefan Korner

Lothar A Doehle

Klaus D Muller

Hermann Schulze-Scholling

A quasi-synchronous information (clocking, data, control signals) transfer between a master unit A and at least one neighbor unit B offers the advantage that one transfer can occur every cycle where any interface delays are tolerated. When the master unit A sends its internal clock along with data and/or control signals to its neighbor unit B, the last named unit receives this clock and derives any and all locally required clocks from this clock. This keeps unit B exactly at the same frequency as unit A, although a phase shift occurs. Unit B also sends its internal clock along with data and/or control signals to unit A. When the clock signals arrive back at unit A, they will have exactly the same frequency as the internal clock of unit A but also an additional phase shift. Compensation of the overall phase shift will be done by a phase alignment means to which all signals are sent on their way to unit A.

Quasi-synchronous information transfer and phase alignment means for

In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation, e.g., processing/logging error data, prior to a processor start. One or more reset areas are defined which are initialized/reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause, e.g., power-on, for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.

Arrangement in a self-guarding data processing system for system

A clock generator system is provided which includes several clock generators each containing a feedback shift register. A parity bit is calculated over the output of all shift registers and compared to an expected value. Additionally, a parity bit is calculated for each shift register, over the bits stored in the shift register, the number of ONE bits in a shift register being constant. A parity error at the output of the shift registers in combination with an error in the additional parity bit allows the correction of the erroneous clock pulse generated by the shift register in error.

Parity-checked clock generator system

A priority control circuit for establishing connections between a data handling system element and a number of subsystems wherein request signals from subsystems are scanned and granted service in a sequence which is determined by their position in a priority ranking order. The scanner returns to the beginning of the order immediately after a request has been granted, the subsystem just serviced being bypassed in the next scan until all of the remaining request signals have been processed. Each time a request signal is encountered and service granted, the scanner returns to the beginning of the order, a new scan is begun and all prior requests serviced are bypassed. In the absence of any other requests or after all of the request signals have been serviced the bypassed subsystems are unlocked and a scan of all requests is begun.

Priority control circuit

An arrangement for the dynamic direct display of pulses in the nanosecond range operates without oscilloscopes or other special display apparatus. To display pulse timing or amplitude characteristics, a pulse sequence is applied to an equidistant tapped delay line, the output from each tap being connected to a bistable storage element with an indicator lamp in the output. A plurality of indicator lamps are arranged in the form of a matrix. If a pulse occurs on a tap during a sampling interval, the associated indicator lamp is turned on. The sequence and identity of the turned on indicators is indicative of the pulse spacing and the pulse width in the pulse sequence.

Dynamic digital pulse display

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Schoenaich, Germany

Peter Rudolph