Infineon Technologies Ag

Siemens Aktiengesellschaft

Robert Boschgmbh

Infineon Technologies LLC

Peter Rohm

Jens Barrenscheen

Patrick Leteinturier

Axel Aue

Gunther Fenzl

Jens Graf

Herman Roozenbeek

Hannes Estl

Angela Rohm, Legal Representative

Rod G Fleck

Dietmar Koenig

Tommaso Bacigalupo

Karl-Heinz Mattheis

Ernst Josef Kock

Hermann Roozenbeek

Michael Erdmann

Berthold Tillmann

Dirk Elkemeier

Jens Dr Barrenscheen

A data communication method for semiconductor chips including transmitting load control data, pilot data and a transmission clock signal from a first semiconductor chip to one or more second semiconductor chips that are each coupled to one or more electrical loads, driving the electrical loads based on a timing defined by the load control data, deriving a transmission rate by dividing the transmission clock signal by a division factor prescribed by the pilot data, and transmitting diagnostic data at the transmission rate from the one or more second semiconductor chips to the first semiconductor chip.

Arrangement comprising a first semiconductor chip and a second semiconductor chip connected thereto

An arrangement including a first semiconductor chip and a second semiconductor chip connected thereto, where the second semiconductor chip is additionally connected to electrical loads and drives these electrical loads on the basis of a timing which is prescribed to it by load control data, and where the first semiconductor chip transmits to the second semiconductor chip the aforementioned load control data and pilot data which control the second semiconductor chip, and where the second semiconductor chip transmits to the first semiconductor chip diagnostic data which represent states prevailing in the second semiconductor chip or events which occur. The diagnostic data are transmitted via a first transmission channel and the load control data and the pilot data are transmitted via a second transmission channel.

An arrangement including a first semiconductor chip and a second semiconductor chip connected thereto, where the second semiconductor chip is additionally connected to electrical loads and drives these electrical loads on the basis of a timing which is prescribed to it by load control data, and where the first semiconductor chip transmits to the second semiconductor chip the aforementioned load control data and pilot data which control the second semiconductor chip, and where the second semiconductor chip transmits to the first semiconductor chip diagnostic data which represent states prevailing in the second semiconductor chip or events which occur. The first semiconductor chip transmits appropriate pilot data in order to prescribe to the second semiconductor chip what transmission rate is to be used by the second semiconductor chip to transmit the diagnostic data to the first semiconductor chip.

A data transmission device forwards data that have been received from a first device, intended for a second device, to the second device. The data transmission device is distinguished in that it has connections for connecting at least two data buses and can output data received by a first data bus either onto the same data bus or onto another data bus immediately or later. Therefore, the data transmission device can be used selectively, alternately or simultaneously as a DMA controller and a bus bridge. It also has additional functions unrelated to DMA controllers and bus bridges.

Data transmission device

An arrangement including a program-controlled unit and a power chip, the power chip connected to drive electric loads in accordance with load control data, and the program-controlled unit transmitting the load control data and power chip control data, and the power chip transmitting to the program-controlled unit diagnostic data. The program-controlled unit, by transmitting corresponding control data to the power chip, can input the behavior of the output drivers of the power chip and/or configure protective mechanisms present in the power chip and/or input to the power chip the format of the diagnostic data to be output and/or input to the power chip when it has to output what diagnostic data and/or input to the power chip which load is to be controlled by which load control data section, and/or input to the power chip whether the load control data contains redundant data suitable for detecting transmission errors.

Arrangement consisting of a program-controlled unit and a power chip connected to it

A control register assembly controls components to be controlled in an electric circuit. The control register assembly includes a control register. The control register is formed by at least one shift register, whose elements are distributed over the electric circuit at mutual intervals, individually or in groups. Such a control register makes it possible to keep short the length of the connecting lines between the control register and the device writing the latter and between the control register and the elements to be controlled thereby.

Control register assembly

The disclosed A/D conversion system is designed to signal the beginning or the impending beginning of an A/D conversion and/or to request the implementation of an A/D conversion from another A/D converter. As a result, it is possible to have a plurality of A/D converters work absolutely time-synchronously with minimal outlay.

A/D converter having signaling and requesting capability

A system and a method are characterized in that the method of detection can be configured by varying a size and/or a position of a time slot to be taken into consideration for the detection and/or by varying relevant bits of the counts to be compared. This makes it possible to individually adapt the detection method to various or varying requirements at any time and with a minimum of expenditure required.

Configuration and method for determining whether the counter reading of a counter has reached a predetermined value or not

A multifunctional electrical control device for producing control signals for driving electrical devices. The control device produces the control signals with a large number of control modules which can be configured with respect to their interaction. This means that the control device is of simple construction, can be used in a variety of ways and can be in each case optimally adapted to the prevailing conditions with a minimum of effort.

Electrical control device with configurable control modules

A timer for an A/D converter generates a request signal for A/D conversion by the A/D converter. In addition to the usual request signal, the timer produces a further signal which is used, before one cycle of the timer has elapsed, to block the A/D converter for low-priority requests from other requesting devices and to reserve it for the timer. In this manner, the signal to be converted from the timer can be sampled at reproducible, equidistant instants without having to wait for the end of the last conversion.

Timer for A/D converter

An electric control device generates control signals that control electrical devices. The control device has a multiplicity of control modules. At least some of the control modules have a comparator for comparing two values and they function in dependence on the various outcomes of comparison. One of more global comparators are provided for certain comparisons in the control device. Each of the global comparators operates on several or all of the control modules. The control modules operate not only in dependence on the comparisons in their respective comparators, but additionally in dependence on the comparison results in the global comparator.

Electric control device

A method and an apparatus for generating clock signals is described, by which a period of time can be subdivided into a desired number of essentially equal-length segments. The method and the apparatus are distinguished in that the clock signals are generated based on the outcomes of a repeated subtraction of a first value from a second value. The first value depends on the number of segments into which the period of time to be subdivided is to be subdivided, and the second value depends on the duration of the period of time to be subdivided.

Method and apparatus for generating clock signals

The invention relates to a method and an arrangement for operating a bus system having at least one master unit and at least one slave unit, having a bus and a bus control unit for the bus arbitration and for controlling the data transfer. The data transmission is split into a request data transfer and a response data transfer, and, in the time between the request data transfer and the response data transfer, the bus is cleared for the data transmissions of other master units in a first data transmission configuration, or the bus is blocked between the request data transfer and the response data transfer, in a second data transmission configuration and slave units. In the case of a response transfer, the master and slave are changed round.

Method and arrangement for data transmission between units on a bus

Th present invention relates to a DMA-controller having a definable plurality of transfer channels. According to the present invention such a unit comprises a data processing unit with a bus interface unit being coupled with a bus for transferring data. The data processing unit executes a data transfer on said bus dependent on programmable parameters. It further comprises a parameter memory storing those parameters for each transfer channel, whereby the parameter memory provides a first memory area which stores for each defined transfer channel a word comprising a vector address to a second memory area comprising specific parameters for said transfer channel.

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Pfaffenhofen, Germany

Peter Rohm