Texas Instruments Corporation

Peter Reinecke

Jim Childers

Hiroshi Miyaguchi

Moo-Taek Chung

Yutaka Takahashi

Jimmie D Childers

Seiichi Yamamoto

An electronic circuit has reduced controller memory requirements for multiple sequential instructions. The electronic circuit includes: a controller memory (1258) with addressable storage locations; a program counter (1548); control logic (1586) for receiving control information from an addressable storage location of the controller memory for performing logical operations on the control information and generating a control signal (1609) responsive to the control information; a repeat counter (1294) for receiving a repeat instruction signal from the controller memory (1258) and for sending a hold count signal (1233) to the program counter (1584) and the control logic (1586) such that the program counter (1584) continues to select the same addressable storage location and the control logic (586) repeats sending the control signal (1609); and a register address counter (1290) for receiving the control signal from the control logic (1586), the hold count signal (1233) from the repeat counter (1294) and a register address signal (1604) from the controller memory. The register address signal stored in the register address counter (1290) points to one of a plurality of registers. The register address counter (1290) receives and stores the address signal if the repeat counter (1294) fail to send the hold count signal and increments the register address signal to point to a next consecutive register if the repeat counter (1294) sends the hold count signal.

Electronic circuit for reducing controller memory requirements

Circuitry and method for performing a double instruction during a single clock cycle in a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The circuitry includes four sense amps per processor element and one ALU to enable reading of four data bits per clock cycle. The method includes reading data from each register file in a processor element and writing the data in one of the register file memory banks; enabling a 2:1 reduction in the amount of required instructions and a substantial reduction in overall cycle time.

Circuitry and method for performing two operating instructions during a

A constant generator is described which provides a sequence of digital constants in a synchronous vector processor. The constant generator includes a constant loop memory for storing data words organized into a plurality of data constant patterns and an end of loop bit, a constant loop counter for supplying sequential addresses to the constant loop memory, and a constant loop counter controller for loading the counter with one of a set of predetermined starting addresses associated with a desired constant pattern stored in the constant loop memory. Additionally, a method of supplying a sequence of digital constants in said constant generator is disclosed and includes the steps of storing a plurality of data words in a plurality of constant patterns, where each constant pattern includes an end of loop bit, supplying an address to the constant loop memory and supplying sequential addresses to the constant loop memory.

Sequential constant generator system for indicating the last data word

An apparatus and method for performing rotation of data in a register file memory. The apparatus utilizes a rotation address generator including rotation value, modulus, and offset registers, a comparator, a data selector, logic circuitry, and a subtractor. A predetermined area (P.times.Q) of the register file memory and a rotation value corresponding to the number of bits to be rotated in the rotation area is designated by an instruction program memory. An instruction decoder signals the register file, modulus register, rotation value register, and offset register of an impending rotation of data, thereby enabling loading of the modulus and rotation value registers and resetting of the offset register. A counter provides a relative address to the comparator and data selector. The comparator compares the relative address with the output of the modulus register, determining whether selected ones of the addressed register file locations fall inside or outside of the rotation area, and send an appropriate signal to the logic circuitry, an OR gate. This OR gate also receives a rotate or not-rotate signal. Consequently, either an absolute address equal to (the value of the relative address-2 * the offset value) mod (8 * the value in the modulus register) or equal to the relative address, based on predetermined conditions, is utilized to access rotationally data from the register file.

Global rotation of data in synchronous vector processor

A synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and is capable of real-time digital processing of video signals. In video applications a data input control circuit including a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit is provided.

Instruction generator architecture for a video signal processor

A synchronous vector processor SVP device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and is capable of real-time digital processing of video signals. The SVP includes interconnecting circuitry enabling the individual processor elements to retrieve data from and transmit data to their first and second nearest neighbors on either side. At the chip level external connections are provided to enable cascading of several SVP devices.

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Lockhart, TX, United States of America

Peter Reinecke