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Mentor Graphics Corporation

Peter Ramyalal Suaris

Yuzheng Ding

Lung-Tien Liu

Nan-Chi Chou

Ashok Vittal

Dongsheng Wang

Memory modules implemented on an FPGA device are re-implemented to improve the performance of the device, such as to reduce logic delays. One or more logic blocks of the FPGA device that realize the logic function of a memory module or portion of a memory module are desirably selected. Based on the outcome of a timing analysis, the most critical signal pin of the selected logic blocks may be identified. Methods of deriving the memory module re-implementation for various types of the most critical pins are disclosed. Procedures are described for integrating physical timing analysis, memory transformation, placement, and routing, as well as for the selection of logic blocks for re-implementation.

Memory re-implementation for field programmable gate arrays

Methods and apparatus for retiming an integrated circuit are described. According to certain embodiments, the retiming comprises performing a timing analysis for one or more paths in the integrated circuit to obtain slack values, selecting one of the paths based on the slack values obtained, and determining a retimeable cut along the path selected. The retimeable cut in these exemplary embodiments comprises a set of input pins for one or more logic instances in the integrated circuit to which one or more retimed sequential elements can be coupled in order to improve the slack value of the path selected. In particular embodiments, the retimeable cut is automatically selected from multiple possible cuts along the path selected. Other embodiments for retiming integrated circuits are disclosed, as well as integrated circuits and circuit design databases retimed by the disclosed methods. Computer-executable media storing instructions for performing the disclosed methods are also disclosed.

Retiming circuits using a cut-based approach

The present invention includes a net topology strategy, referred to as a J-tree model, that meets monotonicity and ring back constraints for nets with bi-directional drivers without much degradation in delay. The present invention includes a method that can be used to automatically construct a J-tree for a given net. A J-tree is generated by identifying at least two clusters of nodes and interconnecting the nodes so that each node has a sibling node that is the same distance from a parent node. Each cluster comprises at least a minimum geometric number of nodes. The nodes are interconnected by first locating a star point for each cluster so that the nodes in each cluster are equidistant from the star point. Then, the star point for each cluster is interconnected forming the topology.

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Camas, WA, United States of America

Peter Ramyalal Suaris