Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V.

Other

Peter Ramm

Reinhold Buchner

Armin Klumpp

Christof Landesberger

Christoph Kutter

Barbara Fr&ouml;schle

Roland Leutenecker

Josef Weber

Bassem Badawi

Nagarajan Palavesam

The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.

Vertical semiconductor diode or transistor device having at least one compound semiconductor and a three-dimensional electronic semiconductor device comprising at least one vertical compound structure

A radio-frequency arrangement is described. The radio-frequency arrangement has a first radio-frequency component, a second radio-frequency component and a wiring substrate having a coaxial radio-frequency line formed in the wiring substrate, wherein the first radio-frequency component and the second radio-frequency component are connected via the coaxial radio-frequency line.

Radio-frequency arrangement having two interconnected radio-frequency components

Embodiments provide a method for manufacturing a microelectronic arrangement. The method includes a step of providing a chip-film module with a semiconductor chip and a film substrate having arranged thereon the semiconductor chip, wherein the chip-film module includes at least one coupling element spaced apart from the semiconductor chip and electrically coupled to at least one terminal of the semiconductor chip. Furthermore, the method includes a step of embedding the chip-film module into a printed circuit board, wherein, in embedding the chip-film module into the printed circuit board, the at least one coupling element of the chip-film module is coupled vertically [e.g. in the vertical direction [e.g. in relation to the printed circuit board]] [e.g. perpendicular to a surface of the printed circuit board] to at least one coupling counter element of the printed circuit board.

Microelectronic arrangement and method for manufacturing the same

Vertical compound semiconductor structure and method for producing the same

A method for manufacturing a three-dimensional, electronic system includes: providing a first integrated circuit structure in a first substrate, wherein the first integrated circuit structure has a first contact pad at a first main side of the first substrate; providing a second substrate with a second main side; forming a vertical contact area in the second substrate; after step (c) forming a semiconductor layer on the second main side of the second substrate; forming a semiconductor device of a second integrated circuit structure in the second substrate with the semiconductor layer; removing the substrate material from a side of the second substrate opposite the second main side, so that the vertical contact area at the opposite side is electrically exposed; arranging the first and second substrates on top of each other aligning the vertical contact area with the contact pad, so that an electrical connection between the first and second integrated circuit structures is produced via the vertical contact area and the contact pad.

Electronic system and method for manufacturing a three-dimensional electronic system

In a method of producing three-dimensional circuits, a first and a second substrate are first provided, each of said substrates having arranged therein a plurality of components which have been tested with regard to their operability. The second substrate is diced so as to obtain a plurality of individual chips, each individual chip comprising at least one component. Subsequently, the individual chips are arranged on the first substrate and connected to said first substrate so that operative components in said first substrate are connected to individual chips including an operative component, and so that non-operative components in said first substrate are connected to chip elements having no function, so as to obtain a three-dimensional complete structure. Finally, the three-dimensional complete structure is diced so as to obtain three-dimensional circuits.

Method for producing three-dimensional circuits

The present invention relates to a method of connecting two semiconductor components comprising the steps of providing in a first main surface of a first semiconductor substrate first component structures including first contact areas, forming in said first semiconductor substrate via holes filled with electrically conductive material and electrically insulated from said first semiconductor substrate, said via holes extending down to the second main surface of the first semiconductor substrate and being connected in an electrically conductive manner to said first contact areas via an electrically conductive connection material on the first main surface of said first semiconductor substrate, forming on the second main surface of the first semiconductor substrate first lands which are connected in an electrically conductive manner to the first contact areas via the electrically conductive material in the via holes, providing on a second semiconductor substrate second component structures including second contact areas, forming second lands which are connected in an electrically conductive manner to the second contact areas, and connecting the first and the second semiconductor substrate in such a way that the electrical as well as the mechanical connection between the two substrates is established via the first and the second lands. By repeating the above-mentioned steps an arbitrary number of times, a three-dimensional integrated circuit can be produced by the method according to the present invention.

Method of vertically integrating electric components by means of back contacting

The invention relates to a wiring method for vertical system integration. According to the method described in the invention, the individual component layers in different substrates are first processed independently of each other in accordance with the state of the art (DE 44 33 846 A1) and then assembled. First, via holes are opened up on the front side of the top substrate which preferably pass through all the component layers present. The top substrate is then thinned from the rear side as far as the via holes, after which a fully processed bottom substrate is joined to the top substrate. Next, the via holes are extended (so-called interchip via holes) as far as a metallized level of the bottom substrate and the contact between the top and bottom substrates is established (wiring). According to the present invention the wiring is carried out in a way which allows for a maximum density of the vertical contacts between the metallization of the top substrate and that of the bottom substrate.

Wiring method for producing a vertical, integrated circuit structure and vertical, integrated circuit structure

In a method for producing a titanium monophosphide layer, a carrier is first placed in a reactor. Thereafter, a TiN layer is deposited on the carrier by supplying TiCl ad NH into the reactor. The TiN layer is annealed immediately after deposition of the TiN layer while PH is supplied to the reactor, in order to form the titanium monophosphide layer on the TiN layer.

Method for producing a titanium monophosphide layer and its use

The invention relates to a method of fabricating a metallized circuit structure for preventing product piracy and product manipulation, a semiconductor component fabricated by the method as well as the use of the semiconductor component in a chip card. The method may be practiced with CMOS-compatible standard Semiconductor technologies and complicates the use of so-called reverse engineering for appropriating foreign technology knowhow or for reading and/or manipulating data stored in the component. It is also possible by the method in accordance with the invention to fabricate a semiconductor component protected from ambient influences. In the method in accordance with the invention the component layer in the substrate (,) is processed up to a metallization complex. Thereafter, the front surface of the component substrate (,) thus obtained is connected to the front surface of a handling substrate (,) and the component substrate (,) is thinned from the rear side. Thereafter, following an appropriate lithographic step, via holes (,) are etched and metallized through the remaining thin component substrate layer down to the areas to be contacted so that electrical contacts to the component are produced.

Method for wiring semi-conductor components in order to prevent product piracy and manipulation, semi-conductors component made according to this method and use of said semi-conductor component in a chip card

A method of making a three-dimensional integrated circuit by transferring fully processed devices from a device layer of first substrate to an auxiliary substrate, separating the auxiliary substrate and the devices thereon into individual chips, testing the chips for their functionality and mounting functioning chips on a carrier substrate in a side-by-side arrangement to form a device layer therein and thereafter mounting a further device layer on said device layer of said carrier substrate. Electrical inter-connection are formed between the devices of said to layers through passage ways in their respective substrates.

Method of making a three-dimensional integrated circuit

A method of fabricating vertically integrated microelectronic systems by CMOS-compatible standard semiconductor process technology, by independently processing individual component layers of at least two separate substrates, including the formation of via holes penetrating through all existing component layers and connecting together the front surfaces of the two substrates, thinning the reverse surface of one of the substrates down to the via holes, increasing the depth of the via holes to a metallization plane of the other substrate and forming electrically conductive connections between the two substrates through the via holes.

Method of vertically integrating microelectronic systems

A method of making a vertical integrated circuit by providing first and second substrates surfaces of which have layers with circuit structures and metallization planes therein, by providing an etching mask on a primary surface of the first substrate, forming via holes in the first substrate extending through the masking surface and the layers of the first substrate, reducing the thickness of the first substrate from a surface opposite its layer surface, alignedly connecting the first substrate by its reduced surface to the layer surface of the second substrate, subsequent deepening of the via holes to the metallization plane of the second substrate and forming electrical interconnection between the metallization planes in the first and second substrates through the via holes.

Method of making a vertical integrated circuit

A method of making a three dimensionally integrated circuit by connecting first and second substrates (1;7) provided with devices in at least one layer in at least one surface in each of said substrates. An auxiliary substrate is connected to the one surface of one of said substrates which is then reduced in thickness from its opposite surface. The auxiliary layer with the devices thereon is then separated into individual chips which after having been found to be functioning are aligned and mounted in a side-by-side arrangement on said one surface of said first substrate. Electrical connection are formed between the devices of the mounted chips and the devices in the first substrate.

Growing community of inventors

Pfaffenhofen, Germany

Peter Ramm