Sandisk Technologies Inc.

Sandisk 3d LLC

Hynix Semiconductor Inc.

Hynix Semiconductor America, Inc.

Skhynix Inc.

Xilinx, Inc.

Hyundai Electronics America, Inc.

Peter Rabkin

Masaaki Higashitani

Jayavel Pachamuthu

Johann Alsmeier

Raghuveer S Makala

Hsingya Arthur Wang

Kai-Cheng Chou

Ashish Kumar Baraskar

Yangyin Chen

Lin Hou

Chen Wu

Mohan Dunga

Kwang-Ho Kim

Deepak Chandra Sekar

Yingda Dong

Franz Kreupl

Venkatesh Ramachandra

Luisa Lin

George Samachisa

Fumiaki Toyama

Roy E Scheuerlein

Christopher John Petti

Yanli Zhang

Gerrit Jan Hemink

Hiroyuki Kinoshita

Wei Zhao

Jagdish Sabde

Perumal Ratnam

Shiqian Shao

Chu-Chen Fu

Jilin Xia

Dae Wung Kang

Jian Feng Chen

Er-Xuan Ping

James K Kai

Xiang Yang

Rahul Sharangpani

Michael J Hart

Tanmay Kumar

Henry Chin

Henry Chien

Andrei Mihnea

Ken Oowada

Dengtao Zhao

Adarsh Rajashekhar

Wipul Jayasekara

Yung-Tin Chen

Changyuan Chen

Yuan Tang

Biswajit Ray

Andrew C Lin

Ming Sang Kwan

Alan Kalitsov

Abhijit Bandyopadhyay

Yuki Mizutani

Satoshi Shimizu

Ramy Nashed Bassely Said

Zhenyu Lu

Zhiyuan Wu

Jongsun Sel

Xiying Chen

Jingyan Zhang

Ming-Che Wu

Jane W Sowards

Wenguang Shi

Katsuo Yamada

Tomoyasu Kakegawa

Min-Hsing Chen

Min-Fang Ho

Haike Dong

Chris Petti

Tim Chen

Frank Qian

Pradhyumna Ravikirthi

A method of forming a bonded assembly includes providing a first semiconductor die containing and first metallic bonding structures and a first dielectric capping layer containing openings and contacting distal horizontal surfaces of the first metallic bonding structures, providing a second semiconductor die containing second metallic bonding structures, disposing the second semiconductor die in contact with the first semiconductor die, and annealing the second semiconductor die in contact with the first semiconductor die such that a metallic material of at least one of the first metallic bonding structures and the second metallic bonding structures expands to fill the openings in the first dielectric capping layer to bond at least a first subset of the first metallic bonding structures to at least a first subset of the second metallic bonding structures.

Bonded assembly including interconnect-level bonding pads and methods of forming the same

A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

Three-dimensional nor array and method of making the same

A memory device includes an alternating stack of insulating layers and control gate layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure containing a memory film and a vertical semiconductor channel located within the memory opening. The memory film includes a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer. The barrier layer may be a dielectric blocking barrier layer.

Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making the same

A three-dimensional memory device containing a plurality of levels of memory elements includes a memory film containing a layer stack that includes a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer, a semiconductor channel, and a control gate electrode.

Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof

A memory device includes at least one instance of a unit layer stack including a source layer, a channel-containing layer that contains a semiconductor channel, and a drain layer that are stacked along a vertical direction over a substrate; a memory opening vertically extending through the at least one instance of the unit layer stack; and a memory opening fill structure located in the memory opening and including a control gate electrode and a memory film in contact with each instance of the semiconductor channel. The memory film includes a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer.

A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.

Bonded assembly containing different size opposing bonding pads and methods of forming the same

A memory device includes a ferroelectric semiconductor channel, a source region contacting a first portion of the ferroelectric semiconductor channel, a drain region located above the source region and contacting a second portion of the ferroelectric semiconductor channel located above the first portion, a word line, and a gate dielectric located between the word line and the ferroelectric semiconductor channel.

Memory device including a ferroelectric semiconductor channel and methods of forming the same

A memory device includes an alternating stack of insulating layers and control gate layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure containing a memory film and a vertical semiconductor channel located within the memory opening. The memory film contains a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer.

A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom electrode, a metal oxide semiconductor vertical transistor channel, a cylindrical gate dielectric, and a top electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

Three-dimensional memory device with vertical field effect transistors and method of making thereof

A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

Bonded assembly including an airgap containing bonding-level dielectric layer and methods of forming the same

A bonded assembly includes a first semiconductor die and a second semiconductor die that are bonded to each other by dielectric-to-dielectric bonding. First conductive via structures vertically extend through the second semiconductor die and a respective subset of the first dielectric material layers in the first semiconductor die, and contact a respective first metal interconnect structure in the first semiconductor die. Second conductive via structures vertically extend through a second substrate and a respective subset of the second dielectric material layers in the second semiconductor die, and contacting a respective second metal interconnect structure in the second semiconductor die. Redistribution metal interconnect structures located over a backside surface of the second substrate electrically connect the first conductive via structures and the second conductive via structures, and provide electrical interconnection between the first semiconductor die and the second semiconductor die.

Bonded assembly including inter-die via structures and methods for making the same

A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.

Three-dimensional memory device including III-V compound semiconductor channel layer and method of making the same

A semiconductor structure includes a bonded assembly of a first semiconductor die including first metal bonding pads and a second semiconductor die including second metal bonding pads, and a capacitor structure including a first electrode, a second electrode, and a node dielectric. The first electrode includes first bonded pairs of metal bonding pads. The second electrode includes second bonded pairs of metal bonding pads. The node dielectric includes portions dielectric material layers laterally surrounding the metal bonding pads.

Capacitor structure including bonding pads as electrodes and methods of forming the same

A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.

Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same

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Cupertino, CA, United States of America

Peter Rabkin