A/n Inc.

Arc International

Nintendo Co., Ltd.

Synopsys, Inc.

Nintendo of America Inc.

Peter R Warnes

Carl Norman Graham

Jeremy E San

Ben Cheese

Thomas Pennello

Richard A Fuhler

Michael Lee Jalkut

Carl N Graham

Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approaches: in one exemplary embodiment, the first approach comprises canonicalizing the 'regular' 32-bit instruction addressing modes, and the second for the 'compressed' 16-bit instruction addressing modes. In another aspect, a plurality of functions (up to and including all available functions) are called indirectly to allow addresses to be placed in a constant pool. Improved methods for instruction selection, register allocation and spilling, and instruction compression are provided. An improved SoC integrated circuit device having an optimized 32-bit/16-bit processor core implementing at least one of the foregoing improvements is also disclosed.

Methods and apparatus for compiling instructions for a data processor

An improved method of optimizing the instruction set of a digital processor using code compression. In one embodiment, the method comprises obtaining an assembly language program to be used for the optimization process; calculating the static frequency of each instruction type from the base instruction set; sorting the instruction types by frequency; determining the number and type of instructions necessary for correct program execution; creating a compressed instruction set encoding; re-evaluating the compressed instruction according to the foregoing steps; and generating an instruction set encoding for the compressed instruction set. Improved compressed instruction formats and register structures useful in a processor are also disclosed. A computer program and apparatus for synthesizing logic implementing the aforementioned data cache architecture and pipeline performance enhancements are further disclosed.

Method and apparatus for processor code optimization using code compression

A video game system is described for use with a television type display device including a host video game system housing a game program processor and a programmable special purpose hardware graphics processor. The programmable graphics processor communicates with the host game processor and incorporates an embedded RAM cache memory. The programmable graphics processor has hardware circuitry for performing 3D geometry transformations such as a 3&#xd7;3 matrix transformation of x, y and z graphics data to provide 3D rotated and/or scaled polygon-based 3D graphic objects and also includes dedicated hardware for plotting individual pixels. The graphics coprocessor utilizes an instruction set that is designed to efficiently implement 3D matrix rotation and scaling operations associated with 3D graphics and also includes special instructions for plotting character-mapped pixels.

External memory system having programmable graphics processor for use in a video game system or the like

A fully programmable, graphics microprocessor is disclosed which is designed to be embodied in a removable external memory unit for connection with a host information processing system. In an exemplary embodiment, a video game system is described including a host video game system and a pluggable video game cartridge housing the graphics microprocessor. The game cartridge also includes a read-only program memory (ROM) and a random-access memory (RAM). The graphics coprocessor operates in conjunction with a three bus architecture embodied on the game cartridge. The graphics processor using this bus architecture may execute programs from either the program ROM, external RAM or its own internal cache RAM. The fully user programmable graphics coprocessor has an instruction set which is designed to efficiently implement arithmetic operations associated with 3-D graphics and, for example, includes special instructions executed by dedicated hardware for plotting individual pixels in the host video game system's character mapped display which, from the programmer's point of view, creates a 'virtual' bit map by permitting the addressing of individual pixels&#x2014;even though the host system is character based. The graphics coprocessor interacts with the host coprocessor such that the graphics coprocessor's 16 general registers are accessible to the host processor at all times.

External memory system having programmable graphics processor for use in a video game system of the like

A fully programmable, graphics microprocessor is disclosed which is designed to be embodied in a removable external memory unit for connection with a host information processing system. In an exemplary embodiment, a video game system is described including a host video game system and a pluggable video game cartridge housing the graphics microprocessor. The game cartridge also includes a read-only program memory (ROM) and a random-access memory (RAM). The graphics coprocessor operates in conjunction with a three bus architecture embodied on the game cartridge. The graphics processor using this bus architecture may execute programs from either the program ROM, external RAM or its own internal cache RAM. The fully user programmable graphics coprocessor has an instruction set which is designed to efficiently implement arithmetic operations associated with 3-D graphics and, for example, includes special instructions executed by dedicated hardware for plotting individual pixels in the host video game system's character mapped display which, from the programmer's point of view, creates a &ldquo;virtual&rdquo; bit map by permitting the addressing of individual pixels&mdash;even though the host system is character based. The graphics coprocessor interacts with the host coprocessor such that the graphics coprocessor's general registers are accessible to the host processor at all times.

Programmable graphics processor for use in a video game system or the like

A fully programmable, graphics microprocessor is embodied in a removable external memory unit for connection with a host information processing system. In an exemplary embodiment, a video game system is described including a host video game system and a pluggable video game cartridge housing the graphics microprocessor. The game cartridge also includes a read-only program memory (ROM) and a random-access memory (RAM). The graphics coprocessor operates in conjunction with a three bus architecture embodied on the game cartridge. The graphics processor using this bus architecture may execute programs from either the program ROM, external RAM or its own internal cache RAM. The fully user programmable graphics coprocessor has an instruction set which is designed to efficiently implement arithmetic operations associated with 3-D graphics and, for example, includes special instructions executed by dedicated hardware for plotting individual pixels in the host video game system's character mapped display which, from the programmer's point of view, creates a 'virtual' bit map by permitting the addressing of individual pixels--even though the host system is character based. The graphics coprocessor interacts with the host coprocessor such that the graphics coprocessor's 16 general registers are accessible to the host processor at all times.

Growing community of inventors

London, United Kingdom

Peter R Warnes