Columbia University

Broadcom Corporation

Celight, Inc.

Peter R Kinget

Tanbir Haque

Shouri Chatterjee

John Wright

Jianxun Zhu

Junhua Shen

Guoxiang Han

Rabia Tugce Yazicigil

Baradwaj Vigraham

Jayanth Kuppambatti

Vivek Mangal

Pieter Vorenkamp

Steven T Jaffe

Harish Krishnaswamy

Isaac Shpantzer

Frank Carr

Myles H Wakayama

Arnoldus Venes

Thinh Cat Nguyen

Aviv Salamon

Yiping Feng

Michael Tseytlin

Nagendra Krishnapura

Alper Demir

Teng Yang

Olga Ritterbush

Daniel J Marz

Yehouda Meiman

Peter Feldman

Kong-Pang Pun

Jaijeet Roychowdhury

Karthik Tripurari

Matthew Bajor

Yannis Tsividis

Ioannis Kymissis

Jacob B Khurgin

Pak Shing Cho

Yaakov Achiam

Mingoo Seok

Shih-An Yu

Israel Smilanski

Daniel De Godoy Peixoto

Marco Crepaldi

Ajay Balankutty

Shravan Siddartha Nagam

Shih-an Yu

Frank Zhang

Yang Xu

Hassan Edrees

Li Guoliang

Joseph Schwarzwalder

Charles Sciabarra

Yudong Zhang

Zhaowen Wang

Xiaofan Jiang

Chunwei Hsu

Circuit for wake-up receivers are provide. In some embodiments, the wake-up receivers include self-mixers that receive a gate bias voltage. Some of the self-mixers are single ended and some are differential. In some embodiments, the wake-up receivers include a matching network that is connected to the input of the self-mixer. In some embodiments, the wake-up receivers include a low frequency path connected to the output of the self-mixer. In some embodiments, the wake-up receivers include a high frequency path connected to the output of the self-mixer. In some embodiments, the wake-up receivers are configured to receive an encoded bit stream. In some embodiments, the wake-up receivers are configured to wake-up another receiver.

Circuits and methods for wake-up receivers

Circuits and methods for multi-phase clock generators and phase interpolators are provided. The multi-phase clock generators include a delay line and multi-phase injection locked oscillator. At each stage of the multi-phase injection locked oscillator, injection currents are provided from a corresponding stage of the delay line. Outputs of the multi-phase injection locked oscillator and provided to mixers which produce inputs to an operational transconductance amplifier which provides feedback to the delay line and the multi-phase injection locked oscillator. The phase interpolator uses a technique of flipping certain input clock signals to reduce the number of components required while still being able to interpolate phase over 360 degrees and to reduce noise.

Circuits and methods for multi-phase clock generators and phase interpolators

Circuits for receivers including: N first mixers that each receive an input signal, are each clocked by a different phase of a first common clock frequency, and each provide an output; and for each N first mixer: a set of M second mixers, wherein each second mixer receives as an input the output of a same one of the N first mixers unique to the set, wherein each of M second mixer is clocked by a different phase of a second common clock frequency, and wherein each second mixer has an output; a set of M resistors having a first side and a second side, wherein the first side is connected to the output of a corresponding one of the set of M second mixers; and a set of M trans-impedance amplifiers that each having an input connected to the second side of a corresponding one of the resistors.

Circuits for intermediate-frequency-filterless, double-conversion receivers

Circuits for a receiver, comprising: M first mixers that each receive an input signal, that are each clocked by a different phase of a first common clock frequency, and that each provide an output, wherein M is a count of the first mixers; and M sets of N second mixers, wherein N is a count of the second mixers in each of the M sets, wherein each second mixer in each set of N second mixers receives as an input the output of a corresponding one of the M first mixers, wherein each of the N second mixers in each of the M sets are clocked by a different phase of a second common clock frequency, and wherein each of the second mixers has an output.

Mechanisms compressive sampling to detect direction of arrival (DoA) of a signal of interest (SoI), comprising: in each of a plurality of receiver paths, receiving the SoI and producing a received signal using an antenna; and using a modulator to: receive a modulator input signal (MIS) based on the received signal produced by the antenna in the path; modulate the MIS at multiple points in time (MPIT) based on different ones of a plurality of pseudo-random numbers; and produce a plurality of modulated output signals in response to the modulating of the MIS at the MPIT; summing across the receiver paths the one of the modulated output signals produced by each of the receiver paths for each of the MPIT, to produce a plurality of sum signals each corresponding to one of the MPIT; and performing a compressed sensing recovery algorithm to recover the DoA of the SoI.

Circuits and methods for using compressive sampling to detect direction of arrival of a signal of interest

Circuits for identifying interferers using compressed-sampling, comprising: a low noise amplifier (LNA); a passive mixer having a first input coupled to an output of the LNA; a local oscillator (LO) source having an output coupled to a second input of the passive mixer; a low pass filter having an input coupled to an output of the passive mixer; an analog-to-digital converter (ADC) having an input coupled to the output of the low pass filter; a digital baseband (DBB) circuit having an input coupled to an output of the ADC; and a compression-sampling digital-signal-processor (DSP) having an input coupled to the output of the DBB circuit, wherein the compression-sampling DSP is configured to output identifiers of frequency locations of interferers, wherein, in a first mode, the LO source outputs a modulated LO signal that is formed by modulating an LO signal with a pseudo-random sequence.

Circuits for identifying interferers using compressed-sampling

Backscatter tags, comprising: antennas; single pole, multiple throw switches each switch (S) having pole terminal connected to one of the antennas, and each having first throw terminal (TT) connected to first side (FS) of inductor (I) for S, second TT connected to FS of capacitor (C) for S, third TT connected to fixed voltage level (FVL), fourth TT that is floating, wherein second side (SS) of I and SS of C are connected to the FVL; power combiner (PC) having inputs connected to fifth TT of each of two of the switches; power detector (PD) having an input connected to output of PC; analog to digital converter (ADC) having input connected to output of PD; hardware processor coupled to output of the ADC and coupled to control terminal of each of the switches.

Systems, methods, and media for multi-antenna, directional backscatter tags

Circuits for continuous-time analog correlators are provided, comprising: a first VCO that receives an input signal and that outputs a first pulse frequency modulated (PFM) output signal; a second VCO that receives a reference signal and that outputs a second PFM output signal; a first phase frequency detector (PFD) that receives the first PFM output signal and the second PFM output signal and that produces a first PFD output signal; a first delay cell that receives the first PFM output signal and that produces a first delayed signal (DS); a second delay cell that receives the second PFM output signal and that produces a second DS; a second PFD that receives the first DS and the second DS and that produces a second PFD output signal; and a capacitor-digital-to-analog converter (capacitor-DAC) that receives the first PFD output signal and the second PFD output signal and that produces a correlator output.

Circuits for continuous-time clockless analog correlators

Circuits for wireless communication on multiple frequency bands are provided. In accordance with some embodiments, transceivers are provided, the transceivers comprising: a first quadrature hybrid having a first in port, a first iso port, a first cpl port, and a first thru port; an antenna coupled to the first in port; a first transmitter having an output coupled to the first cpl port; and a first receiver having an input coupled to the first cpl port.

Circuits for wireless communication on multiple frequency bands

In accordance with some embodiments, polarity-coincidence, adaptive time-delay estimation (PCC-ATDE), mixed-signal techniques are provided. In some embodiments, these techniques use 1-bit quantized signals and negative-feedback architectures to directly determine a time-delay between signals at analog inputs and convert the time-delay to a digital number.

Circuits and methods for time-delay to digital converters

Circuits comprising: a plurality of LNTA branches, each comprising: a cascode common-source (CCS) LNTA, a plurality of passive mixers (PMs), and a plurality of baseband two-stage Miller compensated TIAs (BB2S-TIAs); a plurality of mixer-first branches, each comprising: a plurality of RF switches, a plurality of baseband folded-cascode TIAs (BBFC-TIAs), and a plurality of Cherry-Hooper amplifiers, wherein an input to each of the BBFC-TIAs is provided by an output of at least one of the RF switches, and an input to each of the amplifiers is provided by an output of a corresponding one of the BBFC-TIAs; a first plurality of clock modulators that provide first non-overlapping modulated clocks that are provided to an input of the PMs; and a second plurality of clock modulators that provide a plurality of tri-level modulated mixer clocks that control the switching of the RF switches.

Circuits for modulated-mixer-clock multi-branch receivers

Circuit for wireless communication are provided, the circuits comprising: a first quadrature hybrid having a first in port, a first iso port, a first cpl port, and a first thru port; a first mixer having a first input coupled to the first cpl port and having an output; a second mixer have a first input coupled to the first cpl port and having an output; a third mixer having a first input coupled to the first thru port and having an output; a fourth mixer having a first input coupled to the first thru port and having an output; and a first complex combiner having inputs coupled to the output of the first mixer, the output of the second mixer, the output of the third mixer, and the output of the fourth mixer that provides first I and Q outputs based the output of the first mixer and the output of the second mixer.

Mechanisms for interferer detection can detect interferers by detecting elevated signal amplitudes in one or more of a plurality of bins (or bands) in a frequency range between a maximum frequency (f) and a minimum frequency (f). To perform rapid interferer detection, the mechanisms downconvert an input signal x(t) with a local oscillator (LO) to a complex baseband signal x(t)+jx(t). x(t) and x(t) are then multiplied by m unique pseudorandom noise (PN) sequences (e.g., Gold sequences) g(t) to produce m branch signals for I and m branch signals for Q. The branch signals are then low pass filtered, converted from analog to digital form, and pairwise combined by a pairwise complex combiner. Finally, a support recovery function is used to identify interferers.

Circuits and methods for detecting interferers

The present disclosure relates to a phase-locked loop (PLL) including a frequency detector, a sub-sampling phase detector (SSPD), and a voltage-controlled oscillator (VCO). The frequency detector is configured to receive a reference signal and an output signal, and to generate a coarse-tuning voltage that indicates a frequency difference between the reference signal and the output signal. The SSPD is configured to sub-sample the output signal using the reference signal, and to generate a fine-tuning voltage that indicates a phase difference between the reference signal and the output signal. The VCO is configured to update the output signal based on the coarse-tuning voltage and the fine-tuning voltage.

Compact phase-locked loop with low jitter and reference spurs

Switched capacitor radio frequency receiver front-ends are provided, comprising: a plurality of banks, each comprising: a first switch connected to a RF input signal; a sampling capacitor connected to the first switch and to ground; a second switch connected in parallel to the sampling capacitor; and a Gm cell coupled to the sampling capacitor and an output; wherein: the output of the Gm cell of each of the plurality on banks are coupled together; and the first switch and the second switch are controlled by a multi-phase signal that causes, for each of the plurality of banks, the first switch to be turned ON at a first point in time and the second switch to be turned ON at a second point in time, wherein the first point in time for a first bank is not the same as the first point in time for a second bank.

Circuits for switched capacitor receiver front-ends

Growing community of inventors

Summit, NJ, United States of America

Peter R Kinget