Cirrus Logic Inc.

Peter R Carpenter

Geary L Leger

Bhoopal R Benjaram

Gary L Schaps

John A Wishneusky

Tong Tang

John Andrew Wishneusky

A computer system coupled to a network is disclosed which provides multiple paths for each serial input/output connection. In the receive mode, the current invention separates serial data frames which are composed of sub-functions/channels into sub-function data streams. The sub-function data streams can then be transferred out one at a time. In the transmit mode, the current invention forms data load patterns from the sub-function data streams. Each data load pattern is formed by selecting the appropriate binary bits from the sub-function data streams and arranging the binary bits selected in the sequence desired. The binary bits of each data load pattern are transmitted serially.

System for storing each of streams of data bits corresponding from a

A method and arrangement for shutting off a receive channel in a data communications system to prevent accidental or intentional overwhelming of the memory of the system such as that caused by a continuous burst of short frame data. The data frames received are monitored by a shutoff counter as they are received on one of the channels of a serial input/output (I/O) device. When the shutoff count is reached, the receive channel will be shut off. The current value of the shutoff counter is compared to a value stored in a warning register. Before reaching the shutoff count, a warning is generated when the current shutoff counter value reaches the warning register value.

Method and arrangement for shutting off a receive channel in a data

A method and arrangement for performing direct memory access in a computer system having multi-channel direct memory access (DMA) is provided with a host computer having a main memory and a processor that runs software, a system interface bus coupling the host computer and the main memory, and multiple DMA controllers, on separate chips, coupled to the system interface bus. These multiple DMA controllers provide the system with multiple input/output (I/O) channels. A common buffer pool having a plurality of buffers is accessible to each of the multiple channels for buffering data transferred to or from the host computer. A status queue is also provided, with each entry in the status queue indicating whether a corresponding buffer from the common pool of buffers is a free buffer available for use by one of the DMA channels in a DMA transaction. The status queue is searched for an entry in the status queue which indicates whether its corresponding buffer is a free buffer, when a DMA transaction is to occur over one of the DMA channels. When a free buffer is found, the entry in the status queue and the free buffer are claimed by the DMA channel. The starting address of the free buffer is then determined and data is buffered within the free buffer.

DMA controller arrangement having plurality of DMA controllers and

A method and arrangement for performing direct memory access in a computer system having multi-channel direct memory access (DMA) is provided with a host computer having a main memory and a processor that runs software, a system interface bus coupling the host computer and the main memory, and a multi-channel DMA controller arrangement coupled to the system interface bus and having multiple input/output (I/O) channels. A common buffer pool having a plurality of buffers is accessible to each of the multiple channels for buffering data transferred to or from the host computer. A status queue is also provided, with each entry in the status queue indicating whether a corresponding buffer from the common pool of buffers is a free buffer available for use by one of the DMA channels in a DMA transaction. The status queue is searched for an entry in the status queue which indicates whether its corresponding buffer is a free buffer, when a DMA transaction is to occur over one of the DMA channels. When a free buffer is found, the entry in the status queue and the free buffer are claimed by the DMA channel. The starting address of the free buffer is then determined and data is buffered within the free buffer.

DMA controller having multiple channels and buffer pool having plurality

A pipelined alignment shifter allows transfer of strings of bytes between memories which are non-aligned in computer systems or serial communications and networking with the memories arranged in N fields of B bits, where N and B are integers. The shifter has B copies of N-1 storage elements connected to N copies of N to 1 (N:1) multiplexers. An enable signal E is commonly transmitted to each copy of N-1 storage elements to cause each N-1 storage element, e.g., a latch or a register, to output a previously stored input and to store a corresponding input. A selection signal S indicative of the offset difference between the memories is commonly transmitted to each copy of N:1 multiplexer for realignment of non-aligned boundaries in data transfer mechanisms such as Direct Memory Access (DMA) controllers.

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Watsonville, CA, United States of America

Peter R Carpenter