Infineon Technologies Ag

Peter Pöchmüller

Gunnar H Krause

Justus Kuhn

Michael Schittenhelm

Wolfgang Ernst

Jochen Müller

Jens Lüpke

An integrated memory device including a number of memory blocks including memory cells wherein the memory cells are arranged in a matrix of wordlines and bitlines, wherein the number of memory blocks including a first set of memory blocks the memory cells thereof having a first random access time and a second set of memory blocks the memory cells thereof having a second random access time, wherein the second random access time is smaller that the first random access time.

Integrated DRAM memory device

The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.

Method and device for generating digital signal patterns

In a memory circuit integrated on a semiconductor chip, an interface system is formed between the connection pads and associated internal signal lines and contains a respective separate and complete interface circuit for each of at least two different modes of operation of the memory circuit. Each interface circuit is arranged distributed over a plurality of spaced sections of the chip surface such that sections of different interface circuits alternate with one another. Only the interface circuit which is associated with the mode of operation which is desired when the memory circuit is being used is operatively connected between the connection pads and the associated internal signal lines by metallizations in the topmost metallization plane.

Integrated memory circuit

A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.

System for testing fast synchronous digital circuits, particularly semiconductor memory chips

A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.

Method and device for reading and for checking the time position of data response signals read out from a memory module to be tested

The novel address counter can be used in combination with an existing test unit&#x2014;serving for testing digital circuits&#x2014;for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.

Address counter for addressing synchronous high-frequency digital circuits, in particular memory devices

A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.

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Munich, Germany

Peter Pöchmüller