Infineon Technologies Ag

Other

Siemens Aktiengesellschaft

Peter Poechmueller

Gunnar H Krause

Justus Kuhn

Michael Schittenhelm

Wolfgang Ernst

Jochen Mueller

Jens Luepke

Steffen Loeffler

Armin Reith

The invention relates to an integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, and having a repair circuit for repairing a single bit error in one of the memory cells, the repair circuit comprising: an error memory for storing an item of repair information, an assignment unit in order, when accessing an address of the memory cell array, depending on the repair information, to access either a memory area of the memory cell array or a redundancy memory area, and a test unit for determining the repair information. The test unit comprises a write unit, which successively writes first test data and second test data to a plurality of memory cells of a memory area of the memory cell array, a read-out unit which reads out data stored in the memory area, a modification unit in order to modify the bits of the read-out data in such a way that the position of each bit changes and each of the bits is inverted in order to provide the second test data, which are subsequently written to the memory area with the aid of the write unit, and a comparator unit in order to compare the data read out after the writing of the second test data with expected data and to provide the repair information depending on the comparison result.

Integrated memory circuit and method for repairing a single bit error

The invention relates to a memory circuit comprising regular memory areas and redundant memory areas, redundancy circuits in each case being assigned to the redundant memory areas, each redundancy circuit having permanently settable storage elements in order, in a first setting state, to address the assigned redundant memory area in the event of addressing of the regular memory area with a memory address determined by the first setting state, each redundancy circuit, in a second setting state, addressing the assigned redundant memory area in a manner dependent on an activation signal.

Memory circuit comprising redundant memory areas

In a method for repairing a memory component, data retention times of regular memory cells are determined. Weak regular memory cells having a data retention time that is shorter than a predetermined limit value are determined. A device is programmed in such a manner that a write or read access to the weak regular memory cell is simultaneously also effected for a redundant memory cell in order to jointly read from, or write to, the weak regular memory cell and the redundant memory cell.

Methods for repairing and for operating a memory component

Apparatuses and methods for transmitting and receiving a data signal on a line pair having a first transmission line and a second transmission line are provided. In one embodiment, a data signal which represents the data to be transmitted by means of a sequence of first and second signal levels is applied to the first transmission line, and a reference signal which changes between a first and a second reference level only when a level change between the first and the second signal level is suppressed between two successive signal levels of the data signal on the first transmission line is applied to the second transmission line.

Method for transmission and reception of a data signal on a line pair, as well as a transmission and reception circuit for this purpose

A memory component comprises a plurality of memory cells that are each assigned an address, and an address memory for storing numerical values which are uniquely related to addresses of defective memory cells. An address converter having an input for receiving a first address and an output for outputting a second address is designed in such a way that the second address output at its output is dependent on the first address received at its input and on the numerical values stored in the address memory, each first address being uniquely assigned a second address. An address bus, which is connected to the output of the address converter, transfers the second address to an input of an address decoder, which is designed for selecting a memory cell to which the second address is assigned.

Memory component and addressing of memory cells

The invention relates to a method for testing electrical modules. A test pattern of input signals is applied to each module to be tested as test specimen, and the actual responses of the test specimen to the test pattern is compared with the desired responses. The comparison result is evaluated for the purpose of displaying test assessments. According to one embodiment of the invention, to supply the desired responses, a reference module produced with the same design and technology as the test specimen and tested as entirely satisfactory is utilized. The same test pattern as for the test specimen is applied to the reference module. The invention furthermore relates to circuit arrangements for carrying out this method, in particular for testing data memories.

Method and circuit arrangement for testing electrical modules

The invention relates to a memory module having a printed circuit board; having one or more memory chips which are arranged in a first region of the printed circuit board and are contact-connected by the printed circuit board; having a buffer chip for driving the memory chips and for communicating with a system that is external to the memory module, the buffer chip being arranged in a second region of the printed circuit board and being contact-connected by the printed circuit board; wherein the first and second regions of the printed circuit board are essentially thermally decoupled from one another.

Memory module having memory chips protected from excessive heat

A circuit comprises an output terminal, an output driver for providing an output signal at the output terminal, a switching device for producing one or more connections of the output terminal to a respective fixed or variable potential, and a control device for controlling the switching device, the control device being designed to produce the connection or the connections in the event of a transition in the output signal from a first logic level to a second logic level and to disconnect it at the latest when the output signal attains the second level.

Circuit and method for generating an output signal

A semiconductor device with a test circuit disconnected from a power supply connection to reduce leakage current, and a method of manufacture thereof. The test circuit may be used to test functional circuits on the semiconductor device, and after the tests are completed, the test circuit is disconnected from the power supply connection. The test circuit is powered by contacting a test pad with a probe that supplies power to the test circuit, in one embodiment. In another embodiment, the test circuit is disconnected from the power supply using a laser to blow a fuse in the path of the power supply connection for the test circuit. Optional features include a bleeder device coupled to the power supply input of the test circuit, and logic circuitry for setting the outputs of the test circuit to a predetermined state coupled to the outputs of the test circuit.

Semiconductor device with test circuit disconnected from power supply connection

A system and method are provided for reducing a rate for refreshing a portion of a dynamic random access memory (DRAM). The method includes storing a information for distinguishing between a first portion of a DRAM requiring refresh at a first rate and a second portion of said DRAM permitting refresh at a second rate lower than the first rate. The stored information is then accessed to refresh the first portion of the DRAM at the first rate and to refresh the second portion at the second rate. The information can be generated from post-fabrication stress testing such that most of the DRAM can be refreshed at the lower rate and only the portion requiring more frequent refresh is refreshed at the higher rate.

Self-refresh system and method for dynamic random access memory

Active control of body contacts in memory devices can provide variable substrate voltages during device operation. The body contacts can be used to adjust the body bias of switches in activated memory cells, while maintaining the body bias of switches in inactive memory cells. This can reduce the body effect (i.e., variation of the threshold voltage due to a variation of the substrate or bulk voltage) and can therefore provide improved array device performance (e.g., reduced data corruption) while the word line ('WL') is activated.

Controlled substrate voltage for memory switches

The invention is directed to a device for calibrating signals, whereby at least two signal circuits are provided for generating signals. In order to calibrate the signals, elements are provided that evaluate the signals generated by the signal circuits and, dependent thereon, drive at least one of the at least two signal circuits such that the time reference of the signals generated by the signal circuits relative to one another is set corresponding to at least one prescribed value.

Apparatus and method for calibrating signals

A system, an automatic machine-implemented method, and a machine-readable medium recording a set of instructions to perform such method are provided for de-compacting a layout for a portion of an integrated circuit. According to the method, a spacing is enlarged between neighboring features of a path of a plurality of paths of the layout provided that the length of the path does not then exceed a predetermined dimensional constraint and connectivity is maintained between the neighboring features and any features of the layout to which they are connected. This process is repeated to enlarge at least one other spacing of the layout.

Automated layout transformation system and method

An encoder for encoding a data word with a plurality of bits, wherein the data word is transmittable in parallel on a data bus, wherein one bit line is provided for each bit and wherein each bit may have one of two logical states, including a means for examining the data word in order to determine whether a first number of bits of the data word with a first logical state deviates from a second number of bits of the data word with a second logical state by more than a predetermined threshold, a means for changing the state of a bit of the data word in order to create an encoded data word in case the predetermined threshold is exceeded by the data word, and a means for detecting auxiliary information referring to the changed bit.

Concept for a secure data communication between electronic devices

As disclosed herein, a method and apparatus are provided for amplifying a signal by a transistor of an array of transistors that includes a storage cell transistor array of a dynamic random access memory (DRAM). According to the disclosed method, an array of transistors is provided including transistors of a storage cell transistor array of a dynamic random access memory array. A transistor of the array of transistors has a source or a drain coupled to a fixed potential. An input signal is applied to a gate of the transistor, whereby the transistor amplifies the input signal to provide an output signal appearing on the other of the source or drain of the transistor.

Growing community of inventors

Unterhaching, Germany

Peter Poechmueller