Intel Corporation

Peter Peide Jeng

Jung S Kang

Michael M DeSmith

Yi-Feng Liu

Md Monzur Hossain

A plurality of N-doped strip portions are formed alternating with a plurality of P-doped regions. When a voltage is applied to the N-doped strip portions, a capacitance is created between the N-doped strip portions and the P-doped strip portions. A capacitance is also created between the N-doped strip portions and the underlying epitaxial silicon layer. A larger interface area between N-doped and P-doped regions generally increases the capacitance. By providing the N-doped strip portions, as opposed to a continuous N-doped region, the combined interface area between the N-doped strip portions and the underlying epitaxial silicon layer is reduced. However, more interface area is provided between the N-doped strip portions and the P-doped strip portions. A circuit simulation indicates that junction capacitance per unit peripheral length is 0.41 fF/&#x3bc;m, while the junction capacitance per unit area is 0.19 fF/&#x3bc;m^2. Junction capacitance per unit peripheral length thus scales faster than junction capacitance per unit area.

Intrinsic decoupling capacitor

A camera that includes a battery, a photoflash circuit, and a charging circuit to provide energy from the battery to the photoflash circuit is provided. The camera further includes a voltage monitor coupled to the battery to switch off the battery from the charging circuit when a voltage on the battery falls below a predetermined voltage value. The camera may also include a current monitor, coupled to the battery, to switch off the battery from the charging circuit when a current generated through the battery exceeds a predetermined current value.

Growing community of inventors

Phoenix, AZ, United States of America

Peter Peide Jeng