Alcatel N.v.

Alcatel Radiotelephone

Alcatel

Peter P Reusens

Luc Dartois

Joannes M Sevenhans

Daniel Sallaerts

Paul Marie Spruyt

Lajos Kiss

Stefaan Margriet Van Hoogenbemt

Johan J Haspeslagh

Bernard Biran

Jurgen M Tombal

Jozef D Cannaerts

Hans J Busschaert

Geert Verhenne

Urbain Swerts

Ronny M Van Camp

Etienne Vanzieleghen

Jacques Dulongpont

Eric Huyskens

Marc R De Langhe

A modulator/demodulator (MODEM) is equipped with a rotation circuit (TROT) in its transmitting part (TP) and a rotation circuit (RROT) in its receiving part (RP). To compensate for clock speed differences between the clocks of two communicating modems, the receive rotation circuit (RROT) of one of them rotates the phase of received data carriers in proportion to their respective frequencies. Furthermore, to align transmit data symbols with received data symbols, the transmit rotation circuit (TROT) of one of the modems rotates the phase of the transmit data symbols. Thereto, the phase rotation applied to each carrier whereon the transmit data symbols are modulated, is proportional to the frequency of this carrier and to a phase difference measured between a received pilot carrier (PT) and an expected received pilot carrier (PT.sub.-- E). When the rotation to be applied to a transmit data symbol corresponds to a time shift of half the length of one sample, a sample is duplicated or deleted in a transmit data symbol by transmit skip/stuff circuit (TSS).

Transmitter with phase rotor, modulator/demodulator, communication

The present invention concerns a signal processor module (SPU,AVF) which is adapted to check if a received vector (RV) representing a received signal in a QAM signal vector plane is located in the intersection zone of a first and second zone (ABCDEF,ab) of this signal vector plane. The intersection zone is well chosen so that the phase angle difference (Da) between the received vector (RV) and an expected vector (EV) which represents a signal which should have been received instead of the received signal and which is located in the intersection zone, is limited.

Signal processor module

A Fast Fourier Transform (FFT) dedicated processor includes a scrambler SM scrambling a real input data sequence x(i) and thereby providing two scrambled data subsequences a(i) and b(i). A data generation circuit GC coupled to SM provides a complex data sequence y(i) whose real and imaginary parts equal the scrambled data subsequences a(i) and b(i) respectively. y(i) is applied to an arithmetic unit AU, which under the control of a control unit CoM, is successively converted to an arithmetic means AM, a data regeneration circuit RC and a combinatorial means CM. AM generates an intermediate Fast Fourier Transform series Y(i) of y(i). RC splits up Y(i) into Fast Fourier Transform series A(i) and B(i) of a(i) and b(i) respectively and CM executes a final traditional Fast Fourier Transform combinatorial step and produces the Fast Fourier Transform sequence X(i) of the real input data sequence x(i).

Fast fourier transform dedicated processor

The present invention relates to a for coupling Plain Old Telephone Service (POTS) signals and Asymmetric Digital Subscriber Line (ADSL) signals to a common line (TL). In order to avoid saturation of inductances (L1,L2,L3,L4) of a low pass POTS filter (LPF) located between the POTS transmitter/receiver (PTR) and this common line (TL) when the POTS signal is not sufficiently attenuated by this common line (TL), a variable impedance (SL) is inserted between the POTS transmitter/receiver (PTR) and this low pass POTS filter (LPF). The value of this variable impedance (SL) is controlled by a control signal (CS) supplied by the ADSL transmitter/receiver (ATR) which measures the attenuation caused by this common line (TL).

Signal coupler with automatic common line attenuation compensation

A digital phase locked loop arrangement is used in a desynchronizer demapping a plesiochronous stream from a synchronous bitstream is disclosed to remove jitter due to overhead gapping from the plesiochronous stream. To this end the part of the synchronous bitstream constituting the plesiochronous stream is written into a buffer memory (BUFF), the write address (WRADDR) of which is incremented at the rate of this plesiochronous part. The read address (RDADDR) for the buffer memory (BUFF) is derived from the write address (WRADDR) in the digital phase locked loop arrangement. Herein, a negative feedback for byte justifications in the synchronous bitstream and a positive feedback for bit justifications therein is provided so that byte justifications give rise to a lower change in the incrementing rate of the read address (RDADDR) but of longer duration, whereas bit justifications give rise to an increased change in this incrementing rate but of shorter duration.

Digital phase-locked loop arrangement for use in a desynchronizer

A data transmission system is proposed in which an auxiliary bitstream of low bitrate (AUX) is coded together with a main bitstream of high bitrate (PRIM) without increasing the transmission rate above the high bitrate. This auxiliary bitstream (AUX) is moreover transmitted synchronously with the main bitstream (PRIM). Transmitter (T) divides the main bitstream (PRIM) in periodically occurring blocks of Y bits and codes one bit of the auxiliary bitstream (AUX) in each of the blocks by using a first (AMI) or a second (VAMI) coding law according to the binary value of that bit. The second law is constructed by violating the first coding law (AMI) according to a predetermined violation law. Redundancy in the first coding law (AMI) is used to introduce symbol sequences not permitted under this first coding law (AMI) and to so obtain the second coding law (VAMI).

Data transmission system for synchronously transmitting an auxiliary

A decoder device (VD) used for decoding digital messages according to the Viterbi convolutional decoding algorithm. This Viterbi decoder (VD) may be integrated in a portion of a single electronic chip for inclusion in a receiver of a handportable mobile station of a digital cellular radio system. The decoder (VD) includes a first module (VITALFA) to calculate transition probabilities for the possible state transitions between two successive states of the decoder, and a second module (VIPROB) to calculate, as a function of the state transition probabilities, path probabilities for the possible paths constituted by successive state transitions and ending in each of these states, and to select the path having the highest path probability value. The first/second module (VITALFA/VIPROB) of the device (VD) further calculates a state transition/path bit error rate which is function of the difference between the bits (softbits) received in the first module (VITALFA) and the bits (coded bits) expected for a same state transition/path respectively.

Decoder device for decoding convolutionally encoded message

The present invention concerns an integrated circuit (1) comprising a standard cell (4), an application cell (2) and a test cell (3) designed in particular to store or to modify from outside the integrated circuit the value of communication signals passing between the standard cell and the application cell. The standard cell executing instructions provided on an instruction bus (3B4) by a program memory located in the application cell in response to an instruction address carried by an instruction address bus (3A4), the conductors of these buses constituting communication links. The integrated circuit further includes a branching circuit for replacing at least one erroneous instruction from the program memory with a replacement instruction previously stored in the integrated circuit in response to a predetermined state of the communication links.

Integrated circuit including a test cell for efficiently testing the

A clock signal generator using fractional frequency division is provided comprising a division circuit that produces a clock signal starting from a timing rhythm signal. The frequencies of the two signals are in a division ratio which is the sum of a whole part and a fractional part. A pulse subtractor is provided for receiving the rhythm signal and transmitting it to the division circuit while deleting at least one pulse from this signal upon a command. An accumulator commands a pulse subtractor on each occasion when the product of the number of pulses of the clock signal counted, starting from a time of origin and of the fractional part, changes by unity.

Clock signal generator using fractional frequency division and control

A multi-sample multi-channel digital decimator filter producing a Finite Impulse filtering Response (FIR) from 128 digital filter coefficients for 4 independent channels with a decimation ratio of 32, i.e. each from 1,024 kHz 1-bit inputs to 32 kHz multibit outputs, splits cyclically the coefficient values in 16 groups of 8, according to the coefficient positions, into 4 Read Only Memory modules (0, 1, 2, 3). The Read Only Memory modules are coupled to the 4 multipliers (MULT 0, 1, 2, 3), wherein the coefficient value is multiplied by that of the input bit, through a multiplexer (MUXI) being able to cycle through 4 distinct conditions. The 4 adder accumulators (ACC 0, 1, 2, 3) are coupled to the outputs of their respective channel multipliers. They each partially compute in parallel outputs words using one sixteenth of the coefficients and the multiplexer rotates these words, thereby enabling complete computation in 4 cycles. 4 registers (REG 00, 01, 02, 03) are associated to each adder so as to compute 4 staggered output words simultaneously for each channel. A preferred filtering response can reduce the size of the Read Only Memory modules.

Digital filter and multi-channel decimator

A test device for testing integrated electronic chips (EC) includes: a first processor; an interface for interfacing the first processor with a plurality of other circuits; and a second processor coupled to the first processor. In the test device, at least one of the plurality of other circuits is formed on the integrated electronic chip being tested. The interface includes a first scan path having a first string of first cells formed on the integrated electronic chip. The first string of first cells includes a plurality of serially connected first read buffers, a respective one of the first read buffers being provided in each first cell, for latching data and for transferring data between the at least one circuit of the plurality of other circuits and the first processor. A second scan path includes a second string of second cells, which includes a plurality of serially connected second read buffers, a respective one of the second read buffers being provided in each second cell for latching data and for transferring data between the second processor and the second scan path. The second processor and the first processor are coupled together via a serial interconnection connected between the first and second read buffers. A data transfer device serially transfers latched data from the first read buffer to said second read buffer and visa-versa, at a predetermined transfer rate such that one data transfer is provided at each of a plurality of processor steps of said second processor.

Test device for an electronic chip

A signal generator for generating a modulated output signal from a clock signal. The generator comprises a divider means which derives from the clock signal a square wave having a first fundamental frequency. Means connected to the divider means also provides from the clock signal a rectangular wave signal having a second fundamental frequency that is an even integral multiple of the first fundamental frequency. A chopper chops the square wave signal by the rectangular wave signal to provide the output signal. The frequency content of the spectrum of the output signal is the same as that of the square wave signal.

Digital transmission system

A prior art digital Delta-Sigma converter is improved by including a second control loop with a second forward branch coupled between the first and second subtractor circuits and a third subtractor circuit coupled in series to the first integrator circuit and with a second feedback branch and a third subtractor circuit coupled to the output of said first integrator circuit. When the input signal is equal to zero the output signal of the first integrator circuit will rapidly change to zero because the second control loop applies an additional feedback signal to the third subtractor circuit and therefore also to the first integrator circuit. Because the output signal of the first integrator output circuit signal thus more rapidly varies to zero the same is true for the output signal of the second integrator circuit and therefore also for the converter output signal.

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Laarne, Belgium

Peter P Reusens