Racal-dana Instruments Limited

Peter P Connell

David Brewerton

Malcolm F Morgan

Michael Yeomans

The circuit arrangement described measures the time when a frequency F.sub.o, changing towards a desired frequency value, differs by not more than a predetermined amount (e.g. 100 Hz) from the desired value. Initially F.sub.o is mixed with the sum of 10 MHz and the new desired value for F.sub.o. The lower sideband is selected and thus produces a frequency F.sub.1 which is thus always 10 MHz when F.sub.o reaches its desired value (which may be variable). The circuit therefore has to measure when F.sub.1 comes within 100 Hz of 10 MHz. Initially F.sub.1 is multiplied by a predetermined multiplication factor (.times.100) and the product subtracted from a reference frequency. The latter is the sum of a fixed frequency of 300 KHz and of 10 GHz (i.e. 10 MHz multiplied by 100). This therefore produces an output frequency F.sub.2 whose value differs from 300 KHz by 100 Hz.times.100 (or 10 KHz) when F.sub.1 differs from 10 MHz by 100 Hz. It is therefore a relatively simple matter to determine a 10 KHz difference in 300 KHz, by detecting the output of a filter and comparing this with a reference.

Measurement of elapsed time for a predetermined frequency shift

A synthesizer is disclosed having a frequency modulation phase-locked loop incorporating a voltage controlled oscillator (VCO) producing a 100 MHz, say, carrier which can be frequency-modulated. The VCO output is combined in a mixer with the output of another VCO which is variable stepwise. A frequency divider with a division factor of, say, 10, can be selectively interposed in the output of the VCO by means of a switch, and the resultant divided output is summed with a fixed frequency of, say, 90 MHz so as bring the output back to the 100 MHz carrier frequency. In this way, not only is the FM reduced by a factor of 10 (in this example) but so is the noise.

Frequency modulator including frequency synthesizer

A frequency synthesizer described is made up of cascaded stages each receiving a 10 MHz reference. The first stage has a multiplier producing harmonics in the range 200 to 290 MHz, and any one can be selected by a controllable bandpass filter. A divide by 100 divider feeds an output variable in 100 KHz steps in the range 2 to 2.9 MHz to the next stage. This stage has a multiplier and a bandpass filter which can be set to produce an output variable in 10 MHz steps between 180 and 270 MHz. A divide by ten divider feeds a frequency in the range 18 to 27 MHz into a phase-locked loop also receiving the output from the first stage, so as to set a VCO to produce an output which, after division by a divide by ten divider is variable in 10 KHz steps in the range 2 to 2.9 MHz. Four further stages operate similarly, so that the fourth produces an output variable in 1 MHz steps between 2 and 2.999999 MHz. The seventh or final stage produces an output variable between 20 and 30 MHz in 1 Hz steps. The multipliers and bandpass filters in each stage produce much less noise than would phase-locked loops used for multiplication purposes, and are also more rapidly settable.

Frequency synthesizers

A microprocessor-controlled synthesizer has a low frequency section producing a first output frequency and a comb loop producing a second output frequency. The comb loop includes a multiplier which produces harmonics of 100 MHz one of which is selected and fed to a mixer in a phase-locked loop having a variable divider, the other input of the mixer being a VCO output frequency. At low values of the second output frequency, the phase detector locks to the difference output from the mixer, at higher values to the sum output. The output from the mixer is mixed in a second mixer with the output of a further VCO, and a second phase detector selects the sum output from the second mixer to cover the first half of each decade of MHz and selects the difference output to cover the second half of the decade.

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Marlow, United Kingdom

Peter P Connell