Integrated Device Technology, Inc.

Pmc-sierra Us, Inc.

At+t Corp.

Microsemi Storage Solutions (u.s.), Inc.

Microsemi Solutions (us), Inc.

At&t Intellectual Property I, L.p.

Other

Pmc-sierra, Inc.

Peter Onufryk

Rino Micheloni

Alessia Marelli

Christopher I W Norrie

Ihab Jaser

Raman Gopalakrishnan

Kadangode K Ramakrishnan

Cesar A Talledo

Charles D Cranor

Cormac John Sreenan

Inna Levit

Charles Robert Kalmanek, Jr

David Alan Brown

William Todd Marshall

Alan Edward Kaplan

Alexander Gibson Fraser

Laurence W Ruedisueli

Mike Chan

Thomas Joseph Killian

Richard Vandervoort Cox

Luca Crippa

Norman Loren Schryer

Steven Michael Bellovin

Joseph Henry Condon

Mitrajit Chatterjee

Siukwin Tsang

Ganesh T Seshan

Jayesh Patel

Nelson L Yue

Partho Pratim Mishra

Meng-Kun Lee

Nikolaos Anerousis

Chunfang Xie

Ming Tang

Bruce Scatchard

Tom Reiner

Steven Chau

A processed semiconductor wafer has layered elements that define electrical circuits and a double-seal ring surrounding each individual electrical circuit. The layered elements further define another double-seal ring that surrounds at least two electrical circuits. The processed semiconductor wafer can have additional layered elements that extend each of the double-seal rings that surround individual circuits or, that can extend the other double-seal ring. A method of fabricating such a processed semiconductor wafer. A device comprising two such electrical circuits.

Processed wafer of scalable electrical circuits, method for making same, and device comprising scaled electrical circuits

Methods and apparatus are disclosed for decoding low-density parity check (LDPC) encoded data using a parity check matrix having a plurality of layers. The apparatus includes a decoder having circuitry to decode, layer by layer, a LDPC codeword utilizing functional adjustments and an algorithmic approximation to belief propagation to provide an estimate of the LDPC codeword, the functional adjustments including layer specific parameters for at least two layers of the parity check matrix associated with the LDPC codeword.

Method and apparatus for layer-specific LDPC decoding

A method to decode low-density parity check (LDPC) encoded data using a parity check matrix having a plurality of layers, includes receiving a plurality of values at a decoder. Each value of the plurality of values represents one of a plurality of bits of an LDPC codeword encoded using the parity check matrix. The LDPC codeword is decoded using layered scheduling. A functional adjustment is applied to an approximation of belief propagation used during the decoding. At least one layer specific functional adjustment is used to provide an estimate of the codeword. An apparatus to decode low-density parity check (LDPC) encoded data using a parity check matrix having a plurality of layers includes a decoder. The decoder includes circuitry to decode, layer by layer, the LDPC encoded data utilizing functional adjustments and an algorithmic approximation to belief propagation to provide an estimate of the LDPC codeword. The functional adjustments include layer specific parameters for at least two layers of the parity check matrix associated with the codeword.

Layer specific LDPC decoder

A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.

System and method for higher quality log likelihood ratios in LDPC decoding

A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding.

System and method for accumulating soft information in LDPC decoding

An integrated circuit device for correcting errors in data read from memory cells includes a decoder, an encoder and a data management module. The data management module is configured to select a correctable raw bit error rate limit from a plurality of raw bit error rate limits by changing a code-rate used by the encoder, wherein a virtual change to the decoder and the encoder occur to change the code rate.

Memory controller and integrated circuit device for correcting errors in data read from memory cells

A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of lifetime specific LLR look-up tables representative of the lifetime threshold voltage distribution of the memory storage module, wherein each of the plurality of lifetime specific LLR look-up tables comprises a plurality of LLRs representative of a specific point in the lifetime of the memory storage module for each of the plurality of soft-decision bits. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.

System and method for lifetime specific LDPC decoding

A nonvolatile memory storage controller for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes partitioning circuitry for identifying a set of soft-decision reference voltages having the smallest calculated introduced error value based upon the estimated BER of the nonvolatile memory. The controller further includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value to provide a plurality of soft-decision bits representative of the codeword. The controller further includes an LLR look-up table accessible by the read circuitry to provide LLRs to the LDPC decoder for the subsequent decoding of the codeword.

System and method with reference voltage partitioning for low density parity check decoding

A system and method are disclosed for a flexible routing engine in a PCIe switch. The system may include a switch manager that is enabled, through firmware, to configure one or more routing tables associated with a switch stack of a PCIe switch. To enable non-transparent bridging and non-standard routing, such as mapped I/O routing, the method may include receiving a transaction layer packet at a mapped I/O routed port of a PCIe switch, and performing translation of the requester ID of the packet utilizing tables that are updated by the firmware of the switch manager to route the packet through the switch.

Method and apparatus for mapped I/O routing in an interconnect switch

Apparatuses and methods for correcting errors in data read from memory cells of an integrated circuit device includes an encoder. The encoder is configured from a single parity check matrix and the encoder is configured to be virtually adjustable by setting a number of bits in the encoder to zero. A decoder is configured from the single parity check matrix and the decoder is configured to be virtually adjustable by setting a log-likelihood ratio (LLR) for a number of bits in the decoder to a strong value. A code-rate that the encoder and decoder uses can be changed by adjusting the number of bits in the encoder that are set to zero and the number of bits in the decoder that are set to the strong LLR value.

Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values

Systems and methods for correcting errors in data read from memory cells include a memory controller, which includes an encoder, and a decoder. The memory controller is configured to adjust a correctable raw bit error rate limit to correct different bit error rates occurring in data read from the memory cells. The correctable raw bit error rate limit is adjusted by switching the decoding between hard-decision decoding and soft-decision decoding, wherein a number of soft bits allocated for message values can be changed during soft-decision decoding. The correctable raw bit error rate is adjusted by changing the code-rate within the memory system while making virtual adjustments to the same encoder and decoder.

Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system

A system and method are disclosed for a flexible routing engine in a PCIe switch. The system may include a switch manager that is enabled, through firmware, to configure one or more routing tables associated with a switch stack of a PCIe switch. The method may include receiving a configuration transaction layer packet at the switch manager of a PCIe switch, running firmware at the switch manager to identify a desired behavior of a switch stack of the switch and updating one or more routing tables associated with switch stack.

Flexible routing engine for a PCI express switch and method of use

A system and method are disclosed for a flexible routing engine in a PCIe switch. The system may include a switch manager that is enabled, through firmware, to configure one or more routing tables associated with a switch stack of a PCIe switch. To enable non-transparent bridging and non-standard routing, the method may include receiving a transaction layer packet at a translated routing port of a PCIe switch, and performing translation of the address and requester ID of the packet utilizing tables that are updated by the firmware of the switch manager to route the packet through the switch.

Method and apparatus for translated routing in an interconnect switch

A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein a layer specific attenuation factor is provided for each layer of the LDPC parity check matrix. An attenuation factor matrix comprising a plurality of coefficients specifies the specific attenuation factor for each layer and each iteration of the decoding process. A check node processor performs check node processing for each layer of the parity check matrix associated with the LDPC encoded codeword utilizing the normalized layered min-sum algorithm wherein the attenuation factor of the min-sum algorithm is determined by the coefficients of the attenuation factor matrix.

Layer specific attenuation factor LDPC decoder

A nonvolatile memory controller generates an error correction code for each data unit in a data stripe and generates a parity unit based on the data units of the data stripe. If a data unit of the data stripe has a number of data bit errors not exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller corrects any data bit errors in the data unit based on the error correction code of the data unit. Otherwise, if a data unit of the data stripe has a number of data bit error exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller recovers the data unit based on the other data units of the data stripe and the parity unit.

Nonvolatile memory controller with two-stage error correction technique for enhanced reliability

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Flanders, NJ, United States of America

Peter Onufryk