Bae Systems Information and Electronic Systems Integration Inc.

Wisterium Development LLC

Callahan Cellular LLC

Peter O Luthi

Robert P Boland

Matthew J Thiele

Peter M Simonson

A reconfigurable compute engine interconnect fabric includes a reconfigurable interconnect layer (, FIG.) between an application layer () and a physical layer () which identifies the input and output pins for the engine and their functions.

Reconfigurable compute engine interconnect fabric

A method of operating a multi-level security system including the steps of providing a plurality of processors. At least some of said processors are equipped with a data card which permits simultaneous processing of different classification levels of information and the dynamic reallocation of processors to different classification levels.

Method and apparatus for multi-level security implementation

A reconfigurable compute engine interconnect fabric includes a reconfigurable interconnect layer (FIG.) between an application layer () and a physical layer () which identifies the input and output pins for the engine and their functions.

In a communications or jamming system, accurate timing for the control of the frequency, amplitude, modulation type, pulse repetition rate or other transmit characteristics is achieved for the transmission of digitally processed packetized signals through the use of standard non-realtime off-the-shelf components for the digital processing and a realtime interface which reads transmit chain headers and, with the assistance of a precise time reference, assures that the transmit chain is configured in time to transmit the packets. Note that the realtime interface assures nanosecond timing accuracy regardless of timing errors introduced by the off-the-shelf components used in upstream digital processing.

Method for real time control of transmit chain for software radios

In a communications or jamming system, accurate timing of the transmission of digitally processed signals is accomplished through the use of standard off-the-shelf components. In order to eliminate the need for high-cost, difficult to develop, specific digital hardware or realtime synchronous software not available from the standard off-the-shelf components, the output from the non-real time components is coupled to a realtime interface that assures nanosecond timing accuracy regardless of timing errors introduced by the off-the-shelf components. In one embodiment, the signals to be transmitted are digitized and then packetized, with the data to be transmitted reconstructed using non-real time digital processing. In order to establish the exact time for transmission, the packet is given a time stamp in the form of a header which indicates the exact time at which the packet is to be transmitted by the communications system, with the packet with header being transmitted to a storage buffer, the output of which is coupled to a realtime interface including a precise time output gate, the timing of which is controlled by a precision time reference having nano-second accuracy.

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Nashua, NH, United States of America

Peter O Luthi