Varian Semiconductor Equipment Associates, Inc.

Kla-tencor Technologies Corporation

Applied Materials, Inc.

Kla Tencor Corporation

Peter Nunan

Steven Raymond Walther

Paul Sullivan

Kurt H Weiner

Yuri Erokhin

Sergey D Lopatin

Indranil De

Julian G Blake

Rudy Flores Garcia

Gaurav Verma

David Aitan Soltz

Bernhard Gunter Mueller

Xuena Zhang

Mark Borowicz

Paul S Buccos

Tzu Chin Chuang

Herschel Marchman

Sanjay Tandon

Gregory Redinbo

Bret W Adams

Muhran Nasser-Ghodsi

A method for inspecting a sample with a multi-electron beam inspection system () is described. The method includes: placing the sample on a movable stage () extending in an X-Y-plane; generating a plurality of electron beams () propagating toward the sample; focusing the plurality of electron beams on the sample at a plurality of probe positions () in a two-dimensional array; scanning the sample surface by moving the movable stage in a predetermined scanning pattern while maintaining the plurality of electron beams stationary; and detecting signal electrons emitted from the sample during the movement of the movable stage for inspecting the sample. Further, a multi-electron beam inspection system () for inspecting a sample according to the above method is described.

Method of inspecting a sample, and multi-electron beam inspection system

The present disclosure generally relates to an improved large area substrate thin film transistor device, and method of fabrication thereof. More specifically, amorphous and LTPS transistors are formed by first forming an amorphous silicon layer, annealing the amorphous silicon layer to form polycrystalline silicon, depositing a masking layer over a first portion of the polycrystalline silicon layer, implanting a second portion of the polycrystalline silicon layer with an amorphizing species, and removing the masking layer.

Combo amorphous and LTPS transistors

Apparatuses and methods for manufacturing a solar cell are disclosed. In a particular embodiment, the solar cell may be manufactured by disposing a solar cell in a chamber having a particle source; disposing a patterned assembly comprising an aperture and an assembly segment between the particle source and the solar cell; and selectively implanting first type dopants traveling through the aperture into a first region of the solar cell while minimizing introduction of the first type dopants into a region outside of the first region.

Patterned assembly for manufacturing a solar cell and a method thereof

A particle isolation system includes a semiconductor process chamber; at least one member within the semiconductor process chamber wherein the member has at least a first position and a second position; and at least one isolation compartment having a plurality of walls, the isolation compartment defined by the plurality of walls, at least one of the plurality of walls of the isolation compartment defining at least one opening wherein the member in the first position permits particles to enter the isolation compartment from the semiconductor process chamber through the opening, and wherein the member in the second position substantially encloses the isolation compartment thereby substantially retaining the particles in the isolation compartment and substantially limiting movement of the particles between the semiconductor process chamber and the isolation compartment through the opening. An ion implant system is also provided.

Active particle trapping for process control

A method for wafer bonding two substrates activated by ion implantation is disclosed. An in situ ion bonding chamber allows ion activation and bonding to occur within an existing process tool utilized in a manufacturing process line. Ion activation of at least one of the substrates is performed at low implant energies to ensure that the wafer material below the thin surface layers remains unaffected by the ion activation.

Wafer bonding activated by ion implantation

An approach for providing a cleave initiation using a varying ion implant dose is described. In one embodiment, there is a method of forming a substrate. In this embodiment, a semiconductor material is provided and implanted with a spatially varying dose of one or more ion species. A handler substrate is attached to the implanted semiconductor material. A cleave of the implanted semiconductor material is initiated from the handler substrate at a preferential location that is a function of a dose gradient that develops from the spatially varying dose of one or more ion species implanted into the semiconductor material.

Cleave initiation using varying ion implant dose

A technique for matching performance of ion implantation devices using an in-situ mask. In one particular exemplary embodiment, ion implantation is performed on a portion of a substrate while the remainder is masked off. The substrate is then moved to a second implanter tool. Implantation is then performed on another portion of the same substrate using the second tool while a mask covers the remainder of the substrate, including the first portion. After the second implantation process, parametric testing may be performed on semiconductor devices manufactured on the first and second portions to determine if there is variation in one or more performance characteristics of these semiconductor devices. If variations are found, changes may be suggested to one or more operating parameters of one of the implantation tools to reduce performance variation of implanters within the fabrication facility.

Technique for matching performance of ion implantation devices using an in-situ mask

Various systems configured to reduce distortion of a resist during a metrology process are provided. The systems include an electron beam metrology tool configured to measure one or more characteristics of one or more resist features formed on a specimen. The electron beam metrology tool may be configured as a scanning electron microscope. The resist may be designed for exposure at a wavelength of about 193 nm. One system includes a cooling subsystem configured to alter a temperature of the specimen during measurements by the tool such that the resist feature(s) are not substantially distorted during the measurements. Another system includes a drying subsystem that is configured to reduce moisture proximate the specimen during measurements by the electron beam metrology tool such that the resist feature(s) are not substantially distorted during the measurements. An additional system may include both the cooling subsystem and the drying subsystem.

Systems configured to reduce distortion of a resist during a metrology process and systems and methods for reducing alteration of a specimen during analysis

A method for manufacturing a transistor is provided. The transistor has a substrate with an insulator on the substrate. A structure on the insulator having a structure sidewall is provided with spacers covering a portion of the structure sidewall. An exposed portion of the structure sidewall is activated, and a conformal layer of metal or metal containing material is deposited on the exposed portion of the structure sidewall. The metal or metal containing material is annealed to diffuse into the exposed portion of the structure sidewall to form a salicide.

Method and apparatus for transistor sidewall salicidation

Disclosed is test structure that can be fabricated with minimal photolithography masking steps and in which defects may be localized to specific layers. Mechanisms for fabricating such test structures are also provided. In one embodiment, a semiconductor test structure suitable for a voltage contrast inspection is provided. The test structure includes one or more test layers corresponding to one or more product layers selected from a plurality of product layers of an integrated circuit (IC) product structure. The number of the selected one or more test layers is less than a total number of the plurality of product layers of the product structure, and the test layers include at least a first portion that is designed to have a first potential during the voltage contrast inspection and a second portion that is designed to have a second potential during the voltage contrast inspection. The first potential differs from the second potential. The selected one or more test layers which correspond to product layers are selected from the plurality of product layers such that defects found in the test layers of the test structure during the voltage contrast inspection represent a prediction of defects in the corresponding product structure.

Apparatus and methods for determining and localization of failures in test structures using voltage contrast

Disclosed are methods and apparatus for detecting defects in a partially fabricated semiconductor device with self-aligned contacts. The self-aligned contacts are formed from a first layer with a plurality of contact portions, a second layer with a plurality of conductive lines that are each aligned proximate to an associated underlying contact portion, and a third insulating layer formed over the conductive lines and their proximate underlying contact portions. The third insulating layer has a plurality of vias formed therein that are each formed alongside a one of the conductive lines and over its proximate underlying contact portion. A charged particle beam is scanned over a portion of the vias to form a voltage contrast image of each via. When a minority of the vias in the image have a significantly different brightness level than a majority of the vias, it is then determined that the minority of vias have defects.

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Monte Sereno, CA, United States of America

Peter Nunan