International Business Machines Corporation

Samsung Electronics Co., Ltd.

Advanced Micro Devices Corporation

Oracle International Corporation

Peter Normand Labrecque

Russell J Schreiber

Heechoul Park

Hoyeol Cho

Jungyong Lee

Martin Paul Piorkowski

Myung Gyoo Won

Sumeer Goel

Jinho Kwack

Kiran Koratikere Srinivasa

Atif Habib

A power-supply circuit for a memory includes a bitcell power-supply circuit and a bitcell power-control circuit. The bitcell power-supply circuit includes a first terminal coupled to a bitcell of the memory. The bitcell power-control circuit is coupled to the bitcell power-supply circuit, and controls the bitcell power-supply circuit in a write-assist mode to output a first voltage on the first terminal that is based on a ratio of capacitance of the bitcell and of capacitance of a charge-sharing capacitance. The bitcell power-control circuit further controls the bitcell power-supply circuit in a data-retention mode to output a second voltage on the first terminal that is about one diode drop below a voltage of a main power supply to the bitcell. The bitcell power-control circuit also controls the bitcell power-supply circuit in a power-down mode to turn off power output from the first terminal.

SRAM bitcell supply block with multiple operating modes

Embodiments include systems and methods for improving column selection functionality of memory circuits. Embodiments operate in context of memory bitcells having additional series pass gates (e.g., junction sharing transistors) coupled with a column select signal to form an integrated column select port. Such a column select port can provide each bitcell with column select functionality in a manner that has improved area and power performance over some conventional (added NOR or other logic) approaches. However, the added column select port can still tend to add area, add column select load, and degrade writability (e.g., due to certain charge-sharing effects). Some embodiments are described herein for addressing the area and column select load by sharing certain intermediate nodes among multiple, adjacent bitcells. Other embodiments can include additional ground-connected transistors in a manner that improves writability (e.g., and read noise margin) of the bitcell.

Memory bitcell with column select

Apparatus and methods are provided for accessing memory elements. An exemplary memory element includes an array of memory cells and a control module. Each memory cell of the array is coupled to an access line, wherein the control module is configured to assert a first signal for a write duty cycle on the access line to enable writing to a first memory cell of the array of memory cells, and the control module is configured to assert a second signal for a read duty cycle on the access line to enable reading from the first memory cell. The write duty cycle and the read duty cycle are each selected from a plurality of possible duty cycles. In an exemplary embodiment, the read duty cycle and the write duty cycle are chosen to optimize a performance parameter for the memory element.

Memory elements having configurable access duty cycles and related operating methods

Precharge circuitry for reading a data bit from a memory having at least two local bit lines comprises at least two precharge transistors for precharging the at least two local bit lines, at least two &ldquo;keeper&rdquo; transistors for keeping the at least two local bit lines, and a NAND gate for receiving the data bit from the memory via one of the at least two local bit lines and switching the at least two &ldquo;keeper&rdquo; transistors. The precharge circuitry does not need an additional inverter for switching any of the &ldquo;keeper&rdquo; transistors, thereby eliminating additional capacitance associated with the inverter and reducing unnecessary power consumption associated with the &ldquo;keeper&rdquo; transistors. Preferably, the transistors used in the precharge circuitry are p-channel metal-oxide-semiconductor field effect transistors (MOSFETs).

Circuit and method of selectively activating feedback devices for local bit lines in a memory

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Austin, TX, United States of America

Peter Normand Labrecque