Intel Corporation

Peter Munguia

Adrian R Pearson

Aniruddha P Joshi

Jennifer Wang

Christopher Andrew Thornburg

Steven J Brown

Shrikant M Shah

Gregg Lahti

Steve J Brown

Aditya Katragada

Peter Brink

Kyle D Gilsdorf

Hormuzd M Khosravi

Carl S Marshall

Thomas M Slaight

Edward Butler

Christopher J Cormack

Jason Sandri

John P Lee

Atul Kwatra

Ram R Rao

Monib Ahmed

David Allan Schollmeyer

Suresh Rangarajulu

Techniques are described for providing consistent memory operations and security across electronic circuitry components having disparate memory and/or security architectures when integrating such disparately architected components within a single system, such as a system on chip. A programmable logical hierarchy of isolated memory region (IMR) enforcement circuits is provided to protect such IMRs, allowing or preventing memory access requests from one of multiple distinct circuitry components based on configuration registers for the IMR enforcement circuits. Integration of multiple trust domain architectures associated with the multiple distinct circuitry components is facilitated via trust domain conversion bridge circuitry that includes translation logic for generating information in accordance with a first trust domain architecture based on information provided in accordance with a distinct second trust domain architecture.

Integration of disparate system architectures using configurable isolated memory regions and trust domain conversion bridge

A disclosed example involves managing power states, signing a suspend-to-RAM (STR) data structure by: generating a header key, a scatter/gather table key and a dynamic random access memory (DRAM) key using a root key generated by the secure processor. Generating a header signature using the header key, the header signature based on a table header and a random or pseudo-random value. Generating a scatter/gather table signature using the scatter/gather table key, the scatter/gather table signature based on a scatter/gather table header and a random or pseudo-random value. Generating a DRAM signature using the DRAM key and a value from a region of DRAM. Storing the header signature, the scatter/gather table signature and the DRAM signature in the STR data structure. Resume the processor system from the low-power mode when the data structure is valid based on a comparison of a first signature and a second signature.

Methods and apparatus to protect memory regions during low-power states

In accordance with some embodiments, fuse information may be written into a fuse array in a way that provides sufficient redundancy, making it harder for malicious parties to attack the fuse array.

Redundant fuse coding

A disclosed example method involves configuring a processor to, when transitioning the processor system to a low-power mode, use a key and a random or pseudo-random value to generate a first signature based on a sample of memory regions to be protected during the low-power mode, the memory regions based on a manufacturer required regions table and a third-party required regions table. The disclosed example method also involves configuring a processor to, during a resume process of the processor system from the low-power mode, generate a second signature based on the sample of the memory regions protected during the low-power mode. The disclosed example method also involves configuring a processor to, when the first signature matches the second signature, cause the processor system to resume from the low-power mode, and when the first signature does not match the second signature, generate an error.

A disclosed example method involves when transitioning a processor system to a low-power mode, generating at least a first signature based on a data structure storing memory addresses of memory regions to be protected during the low-power mode. During a resume process of the processor system from the low-power mode, at least a second signature is generated based on the data structure storing the memory addresses of the memory regions to be protected during the low-power mode. When the first signature matches the second signature, the processor system resumes from the low-power mode. When the first signature does not match the second signature, an error is generated.

An embodiment uses hardware secrets secured within a security engine to provide a secure solution for field key provisioning. An embodiment is operating system independent due to the out-of-band communications with the security engine. Secrets need not be provisioned during manufacturing time. An embodiment may ensure only security engine specific provisioned secrets are used at runtime. Other embodiments are addressed herein.

Secure remote credential provisioning

Various embodiments for providing datapath security in a system-on-a-chip (SOC) device are described. In one embodiment, an apparatus may comprise a security controller to configure one or more functional units connected to a shared on-chip bus embedded in an SOC device to communicate with other functional units through one or more secure datapaths. The one or more functional units may be arranged to encrypt clear data, send encrypted data out through a secure datapath, receive encrypted data in from a secure datapath, and decrypt the encrypted data to recover clear data. Other embodiments are described and claimed.

Systems and techniques for datapath security in a system-on-a-chip device

Methods and arrangements to extend message signal interrupt (MSI) transactions with additional data to reduce the latency associated with servicing interrupts included in the transactions are contemplated. Some embodiments may comprise a chipset that transmits the MSI to a processor to service the interrupt. The chipset may identify that a transaction is an extended MSI transaction by determining that the MSI has more than a four bytes. In several embodiments, the chipset may validate the MSI by determining that the MSI comprises at least six bytes and, in further embodiments, by determining that the extended MSI has a valid signature byte. Another embodiment comprises a processor to receive the extended MSI transaction and store the data to service the corresponding interrupt(s) in a low latency buffer. The processor may then service the interrupt(s) based upon the data when the processor becomes available.

Extended message signal interrupt

A method and device for combining packets is disclosed. In various embodiments, a plurality of packets that are compliant with a particular protocol are combined into a single packet of the same protocol. The single packet also preserves identification information for each of the combined packets within the single packet. The identification information can be used to partition and/or route the combined packets to their respective destinations.

Packet combining on PCI express

An embodiment involves throttling a bus frequency based upon incoming arbitration requests from units or devices coupled to a bus. Arbitration circuitry monitors request rates from each requestor and increases or decreases the bus frequency in order to meet the bandwidth levels requested. When the bandwidth requirements increase, the bus frequency increases. When the bandwidth requirements are reduced, the bus frequency is reduced to reduce power consumption. No software intervention is required to adjust the bus bandwidth.

Apparatus for adjusting a clock frequency of a variable speed bus

A discussion of a local memory with at least a command block section and a cache section that facilitates an efficient interrupt processing. The command-block section is allocated on a per interrupt basis and contains pointers to cache-lines. When an interrupt is recognized an interrupt, the proposal uses the pointers in the command-block to prefetch the corresponding cache-lines from the cache section of the local memory, which it loads into its local cache buffer. Thus, when the CPU recognizes an interrupt, the information for the context-switch is already available in cache.

Method, apparatus, and a system for efficient context switch

A method and apparatus to generate one or more graphics textures of a video image, wherein graphics textures have differing resolutions, and to render the video image as a graphics texture using the one or more graphics textures of differing resolutions. The one or more graphics textures have different resolutions, for example, a base resolution and one or more scaled resolutions. The graphics texture may be rendered and displayed on a surface of a multi-dimensional graphics object that may be manipulated on a display.

Apparatus and method for rendering a video image as a texture using multiple levels of resolution of the video image

A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of devices, and are accessible through the second bridge. A hub interface allows data to transfer downstream from the first bridge to the second bridge, and allows data to transfer upstream from the second bridge to the first bridge. A controller, external to the first and second bridges, accesses the configuration registers via the second bridge. A logic device allows the second bridge to send data to, and receive data from, the controller.

Method and apparatus for generating traffic in an electronic bridge via a local controller

A variable speed bus has its frequency adjusted based upon bandwidth requirements of active units coupled to a variable speed bus. As units coupled to the bus are stopped, bandwidth requirements are lowered and the bus frequency is reduced in response to the lowered bandwidth requirements. An arbiter selects an appropriate arbitration configuration based on which units are active and which are stopped. The arbitration configuration is adjusted to ensure that the bandwidth requirements of the active units are sustained despite the reduced clock frequency.

Growing community of inventors

Chandler, AZ, United States of America

Peter Munguia