International Business Machines Corporation

Other

Ruggli Projects Ag

Peter Mueller

Thomas E Morf

Evangelos Stavros Eleftheriou

Roman Alexander Pletka

Walter Heinrich Riess

Ioannis Koltsidas

Robert Haas

Heike E Riel

Theodoros A Antonakopoulos

Aspasia Palli

Marcel A Kossel

Pier Andrea Francese

Tilman A Beierlein

Mridula Prathapan

Cezar Bogdan Zota

Xiaoyu Hu

Kilian Rolli

Matthias Mergenthaler

Armin Beck

Horst Vestweber

Siegfried Friedrich Karg

Stephan Paredes

Ute Drechsler

Tobias Blaettler

Roland Germann

Paul F Seidler

Andreas Fuhrer Janett

Matthias Braendli

Bogdan Cezar Zota

Eunjung Cha

Axel Hammen

Santos F Alvarado

Roland W Widmer

Beat Ruhstaller

Heinz Graber

Viktor Madl

Brian K Crone

Lieike Riel

Provided is a low noise amplifier circuit for a quantum computer. The low noise amplifier circuit comprises a plurality of input stages, a shared output stage, and a voltage controller. Each input stage is coupled to one or more qubits. The shared output stage is coupled to the plurality of input stages. The voltage controller is coupled to the plurality of input stages and the shared output stage. The voltage controller is configured to selectively activate an input stage of the plurality of input stages in order to read a qubit coupled to the input stage.

Parallelized low noise amplifiers for a quantum computer

A superconductor transistor structure includes a source electrode and a drain electrode on a same plane as the source electrode. There is a channel region on top of the source and drain electrodes and configured to carry a current. A gate structure comprising a metallic material is on top of the channel region. The source and drain are located on a side that is opposite to that of the gate structure, with respect to the channel region.

High electron mobility transistor with source and drain electrodes below the channel

A computer-implemented method of reducing an impact of stray magnetic fields on components of a quantum computing chip is disclosed. The computer implemented method includes applying a first current signal to a first component of a quantum computing chip, whereby the first component generates a stray magnetic field impacting an operation of a second component of the quantum computing chip. The computer implemented method further includes applying a compensation current signal to a shielding circuit of the quantum computing chip, the compensation current signal generated according to a predetermined function of the first signal, to magnetically shield the second component from the stray magnetic field generated by the first component.

Semi-active magnetic shielding for qubit unit components of quantum computing apparatuses

The invention relates to a control unit for controlling a data transfer between a classical processor and a quantum processor with a plurality of qubits. The control unit comprises a plurality of control and read-out circuits configured for controlling and reading out the plurality of qubits. Each of the control and read-out circuits is assigned to one or more of the qubits. A controlling of the quantum processor by the control unit comprises selectively powering on a subset of the control and read-out circuits during an instruction cycle, while ensuring that the remaining control and read-out circuits are powered off during the instruction cycle. The powered-on subset of control and read-out circuits is used to control a subset of the qubits and to read out data from the subset of qubits.

Control unit for qubits

An electrostatic discharge (ESD) protection circuit is configured to protect a target circuit that operates in a cryogenic temperature is provided. The ESD protection circuit connects a terminal of the target circuit and a ground potential with no connection to a bias potential. When the ESD protection circuit receives a voltage potential at the terminal of the target circuit, the ESD protection circuit (i) disallows electrical current to flow through from the received voltage potential when the device is at a cryogenic temperature and (ii) allows electrical current to flow through from the received voltage potential when the device is at a room temperature.

Semiconductor quantum device ESD protection

A method of modifying a resonant frequency of a quantum device includes generating an ion beam having a beam energy and exposing a surface of the quantum device to the ion beam for an exposure time. The ion beam is incident onto the quantum device at an oblique angle that is less than 90 degrees as measured from the surface of the quantum device. The quantum device includes a Josephson junction, the ion beam exposing the quantum device proximate to the Josephson junction to modify a property of the Josephson junction, the property being associated with the resonant frequency of the quantum device.

Ion milling for frequency tuning of superconducting qubits

Systems and methods directed to a quantum processing apparatus are provided. The apparatus comprises M solid-state qubits, where M&#x3e;1, and control electronics, which are connected to the solid-state qubits. The control electronics comprise one or more qubit readout circuits, where each of the qubit readout circuits is connected to at least one of the solid-state qubits and comprises a downsampling analog-to-digital converter (hereafter DSADC). Each DSADC is configured to downsample analog signals obtained from the at least one of the solid-state qubits. Such a DSADC operates in the nNyquist zone of the spectrum of the analog signals obtained, so as to down-convert such analog signals from the nNyquist zone to the mNyquist zone of the spectrum, where n&#x3e;m&#x2265;1, prior to sampling the analog signals to convert them into digital signals, in operation. One or more embodiments of the invention are further directed to a related method of operating such a quantum processing apparatus.

Quantum processing apparatus with downsampling analog-to-digital converter

A quantum processing system may include one or more superconducting qubits and a qubit controller for controlling the one or more qubits. The qubit controller includes a radio frequency generation unit comprising electronic components, which are altogether configured to generate modulated RF signals. The controller also includes a phase locked loop unit maintaining a reference clock for two or more of the components of the RF generation unit, and a timing controller including an absolute timing register, the latter accessed by the reference clock, in operation. The qubit controller comprises a sequencer coupled to the timing controller to synchronize said two or more of said components by maintaining a coherent signal for said two or more of said components, the coherent signal phase matched to the one or more qubits, to drive and/or read out the one or more qubits via modulated signals generated by the synchronized components, in operation.

Quantum processing system including a modulated RF generator with synchronized components

A quantum computer hardware apparatus may include a first stage, which is connected to one or more signal generators, and a second stage adapted to be cooled down at a lower temperature than the first stage. Superconducting qubits are arranged in the second stage. The signal generators are configured, each, to generate radio frequency (RF) signals to drive the qubits, in operation. The apparatus may further include an intermediate stage between the first stage and the second stage, wherein the intermediate stage comprises one or more coolable filters, the latter configured for thermalizing RF signals from the signal generators. Related methods for thermalizing radio frequency signals in a quantum computer hardware apparatus are also disclosed.

Quantum computer hardware with reflectionless filters for thermalizing radio frequency signals

A superconducting circulator device and method of operation. The superconducting circulator device comprises more than two resonators of equal static resonance frequency chained to a ring system by strong coupling. Each of the resonators comprises an adjustable inductor built into the each one of the resonators. The device comprises also a set of ports, each one of the ports coupled to a corresponding one of the more than two resonators, a set of modulators, each one of the modulators positioned adjacently to a corresponding one of the adjustable inductor, and a set of modulation control ports. Each of the modulation control ports is connected to a corresponding modulator of the set of modulators such that each of the modulation control ports controls the related static resonance frequency of the related resonators and such that the ring system is modulatable.

Circulator for use in superconducting quantum technology

A superconducting circulator device may be provided. The superconducting circulator device comprises more than two resonators of equal static resonance frequency chained to a ring system by strong coupling. Each of the resonators comprises an adjustable inductor built into the each one of the resonators. The device comprises also a set of ports, each one of the ports coupled to a corresponding one of the more than two resonators, a set of modulators, each one of the modulators positioned adjacently to a corresponding one of the adjustable inductor, and a set of modulation control ports. Each of the modulation control ports is connected to a corresponding modulator of the set of modulators such that each of the modulation control ports controls the related static resonance frequency of the related resonators and such that the ring system is modulatable.

A tampon with an absorbent body of which at least a part of its volume is made from an absorbent material and having a middle part, a distal end and a proximal end, and which is connected to an extraction device. The volume of absorbent material in such a tampon is designed to absorb between 0.5 g and 4 g, preferably 3.5 g, of liquid.

Tampon for days between menstruation

A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.

Storage device with 2D configuration of phase change memory integrated circuits

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Zurich, Switzerland

Peter Mueller