Qimonda Ag

Infineon Technologies Ag

Globalfoundries Inc.

Peter Moll

Odo Wunnicke

Till Schloesser

Kai Frohberg

Heike Scholz

Harald Seidl

Martin Gutsche

Dietmar Temmler

Christoph Nölscher

Kristin Schupke

Johannes Heitmann

Peter Baars

Rolf Weis

Bernhard Sell

Matthias Goldbach

Daniel Fischer

Stephan Kudelka

Hans-Juergen Thees

Dirk Manger

Stephan Wege

Klaus Muemmler

Stefan Jakschik

Carsten Hartig

Dominik Olligs

Peter Lahnor

Dominic Thurmer

Andreas Orth

Annette S&auml;nger

Matthias Ruhm

Martin Schmidt

Stefan Thierbach

Stefan Rongen

Andreas Schuring

Guido Überreiter

Srivatsa Kundalgurki

Methods for in-die overlay reticle measurement and the resulting devices are disclosed. Embodiments include providing parallel structures in a first layer on a substrate; determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements; forming overlay trenches, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures; determining a trench center-of-gravity of an overlay trench; determining a structure center-of-gravity of a structure exposed in the overlay trench; and determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity.

Method for in-die overlay control using FEOL dummy fill layer

The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

Method of forming a semiconductor device and according semiconductor device

A method of reducing the impact of FEoL topography on dual stress liner depositions and the resulting device are disclosed. Embodiments include forming a first nitride layer between and over a pFET and an nFET; thinning the first nitride layer; forming a second nitride layer over the first nitride layer; and removing the first and the second nitride layers from over the pFET.

Tensile nitride profile shaper etch to provide void free gapfill

Integrated circuits with close electrical contacts and methods for fabricating such integrated circuits are provided. The method includes forming a first and a second contact in an interlayer dielectric, and forming a recess between the first and second contact. A etch mask is formed overlying the interlayer dielectric, and the etch mask is removed from over a recess mid-point. A center contact is formed in the interlayer dielectric at the recess mid-point.

Integrated circuits with close electrical contacts and methods for fabricating the same

The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.

Method for producing a structure on the surface of a substrate

In a method for fabricating a capacitor that includes an electrode structure (), an auxiliary layer () is formed over a substrate (). A recess (), which determines the shape of the electrode structure (), is etched into the auxiliary layer (), and the electrode structure of the capacitor is formed in the recess. As an example, the auxiliary layer can be a semiconductor layer ().

Method for fabricating a capacitor

A method for forming an integrated circuit having openings in a mold layer and for producing capacitors is disclosed. In one embodiment, nanotubes or nanowires are grown vertically on a horizontal substrate surface. The nanotubes or nanowires serve as a template for forming openings in a mold layer. The substrate is covered with a mold material after the formation of the nanowires or nanotubes. One embodiment provides mold layers having openings with a much higher aspect ratio.

Methods for forming an integrated circuit, including openings in a mold layer from nanowires or nanotubes

A storage capacitor includes a first capacitor portion and a second capacitor portion, the second capacitor portion being disposed above the first capacitor portion, thereby defining a first direction. The first and the second portions each include a hollow body made of a conductive material, respectively, thereby forming a first capacitor electrode. An upper diameter of each of the hollow bodies is larger than a lower diameter of the hollow body, the diameter being measured perpendicularly with respect to the first direction. The storage capacitor also includes a second capacitor electrode and a dielectric material disposed between the first and the second capacitor electrodes. The storage capacitor also includes an insulating material disposed outside the hollow bodies, and a layer of an insulating material. A lower side of the insulating layer is disposed at a height of an upper side of the first capacitor portion.

Storage capacitor, a memory device and a method of manufacturing the same

A method for forming a capacitor structure, according to which the following consecutive steps are executed: providing a substrate having on its surface contact pads and a dielectric mold provided with at least one trench leaving exposed the contact pads; forming a first conductive layer on side walls of the trench in a top region of the trench the conductive layer being without contact to the contact pads; depositing a first dielectric layer; depositing a second conductive layer on the contact pad and on the side walls of the trench; depositing a second dielectric layer; depositing a third conductive layer; and forming a vertical plug interconnecting the first conductive layer and the third conductive layer.

Method for forming a capacitor structure

A method for manufacturing a capacitor electrode structure, according to which the following steps are executed: A substrate is provided, which comprises contact pads arranged in lines and rows on a surface of the substrate. The lines are non-parallel to the rows. A first mold is applied on the substrate. At least one first trench is formed into the first mold above the contact pads. The first trench spans over at least two contact pads arranged in one row. A first dielectric layer is applied on side walls of the at least one first trench for forming first supporting walls. A second mold is applied on the substrate. At least one second trench is formed into the second mold above the contact pads. The second trench spans over at least two contact pads arranged in one line. A second dielectric layer is applied on side walls of the at least one second trench for forming second supporting walls. And a conductive layer is applied on the first and second supporting walls for forming a first electrode of the capacitor structure.

Method for manufacturing a capacitor electrode structure

The present invention relates to a stacked capacitor array and a fabrication method for a stacked capacitor array having a multiplicity of stacked capacitors, an insulator keeping at least two adjacent stacked capacitors mutually spaced apart, so that no electrical contact can arise between them and the stacked capacitors are mechanically stabilized.

Stacked capacitor array and fabrication method for a stacked capacitor array

A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of a backside electrode encloses the pad-shaped section of the storage electrode. An upper section of the backside electrode is enclosed by the cup-shaped upper section of the storage electrode. A first capacitor dielectric separates the lower sections of the backside and the storage electrodes. A second capacitor dielectric separates the upper sections of the backside and the storage electrodes. The electrode area of the capacitor is enlarged while the requirements for the deposition of the capacitor dielectric are relaxed. Aspect ratios for deposition and etching processes are reduced.

Storage capacitor for semiconductor memory cells and method of manufacturing a storage capacitor

A method produces stacked capacitors for dynamic memory cells, in which a number of trenches () are formed in the masking layer (), each trench () being arranged above a respective contact plug () and extending from the top () of the masking layer () to the contact plugs (). A conductive layer () covers the side walls () of the trenches () and the contact plugs () in order to form a first electrode () of a stacked capacitor (). In an upper region (), which is remote from the contact stack (), the conductive layer () is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.

Stacked capacitor and method for producing stacked capacitors for dynamic memory cells

The invention relates to a method for trench etching, in particular a method for anisotropic deep trench (DT) etching in an Si substrate by plasma dry etching, such as reactive ion etching (RIE), magnetically enhanced RIE or inductively coupled plasma etching (ICP), and sidewall passivation of the etched trenches in the Si substrate, the Si substrate being provided with an etching mask before the beginning of the etching operation. The invention is intended to provide a method for depth etching which, with a low outlay, makes it possible to achieve a significantly larger etching depth at higher speed and which enables a further reduction of the structure widths without any difficulty. This is achieved by virtue of the fact that a DT etching step into the Si substrate ( ) as far as a predetermined etching depth is performed, in that the redeposit ( ) produced during the DT etching step is replaced by a protective layer for the sidewall passivation, and in that the sequence of these steps is repeated until the envisaged target depth of the trench ( ) is reached, a break-through ( ) being etched through the protective layer at the bottom of the trench ( ) before each further DT etching step.

Growing community of inventors

Dresden, Germany

Peter Moll