General Electric Company

Momentive Performance Materials Gmbh

Morpho Detection, Inc.

Gelcore, LLC

Abb Schweiz Ag

Peter Micah Sandvik

Stephen Daley Arthur

Steven Francis LeBoeuf

Kevin Sean Matocha

Vinayak Tilak

Avinash Srikrishnan Kashyap

Mark Philip D'Evelyn

Dong-Sil Park

Kristi Jean Narang

Larry Burton Rowland

Huicong Hong

James Jay McMahon

Jeffrey Bernard Fedison

Dale M Brown

David Mulford Shaddock

James William Kretchmer

James Wilson Rose

Edward Brittain Stokes

Emad Andarawis Andarawis

Jody Alan Fronheiser

Peter Almern Losee

Ljubisa Dragoljub Stevanovic

Rui Zhou

Stanton Earl Weaver

Zachary Matthew Stum

Alexey V Vert

Stanislav Ivanovich Soloviev

Elena Babes-Dornea

Renyan Qin

Siddharth Rajan

Sabarni Palit

Alexei Vertiatchikh

Joe Walter Kirstein

Radislav Alexandrovich Potyrailo

Jesse Berkley Tucker

Thomas Edward Johnson

James Anthony Ruud

Stanton Earl Weaver, Jr

Ching-Yeu Wei

Alexander Viktorovich Bolotnikov

John Patrick Lemmon

Deborah Ann Haitko

Anthony Yu-Chung Ku

Sergei Ivanovich Dolinsky

Richard Dale Slates

Anis Zribi

Sergio Paulo Martins Loureiro

Jonathan David Short

Wei-Cheng Tian

Loucas Tsakalakos

Steven Alfred Tysoe

Venkatesan Manivannan

Kenneth Roger Conway

Jonathan Lloyd Male

Azar Alizadeh

Mark Allen Woodmansee

Nikhil Taskar

Suryaprakash Ganti

Abasifreke Udo Ebong

Xian-an Cao

Stanton E Weaver

Samer Aljabari

Xingguang Zhu

Ho-Young Cha

Dal Marius Brown

Pradeep Sharma

Mark Gerard Roberto

Peter Almren Losee

Kashyap,avinash Srikrishnan

James Mcmahon

A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

Method and system for a semiconductor device with integrated transient voltage suppression

A transient voltage suppression (TVS) device and a method of forming the device are provided. The transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. The TVS device also includes a conductive path electrically coupled between the second layer and an electrical connection to a circuit external to the TVS device, the conductive path configured to permit controlling a turning on of the TVS device at less than a breakdown voltage of the TVS device.

Method and system for transient voltage suppression devices with active control

A solid state photomultiplier includes at least one microcell configured to generate an initial analog signal when exposed to optical photons. The solid state photomultiplier further includes a quench circuit electrically coupled with the at least one microcell. The quench circuit includes at least one quench resistor configured to exhibit a substantially constant temperature coefficient of resistance over a selected temperature range.

Solid state photomultiplier with wide temperature range of operation

A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Semiconductor assembly and method of manufacture

A method of fabricating an overvoltage protection device and an over-voltage circuit protection device are provided. The over-voltage circuit protection device includes a plurality of transient voltage suppression (TVS) devices coupled in electrical parallel.

Method and system for over-voltage protection using transient voltage suppression devices

Embodiments of a photodiode array are provided herein. In some embodiments, a photodiode array may include a semiconductor layer configured to convert photons into analog electrical signals; and a passive layer having a first surface and a second surface disposed opposite the first surface, wherein the semiconductor layer is coupled to the first surface, and wherein the passive layer is configured to have a signal receiving component coupled directly to the second surface of the passive layer.

Photodiode array for imaging applications

A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon carbide (SiC), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Over-voltage protection of gallium nitride semiconductor devices

A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (&#x3bc;m) and 22.0 &#x3bc;m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.

Method and system for transient voltage suppression

A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.

Method and system for transient voltage suppressors

A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.

Heterostructure device and associated method

System for transient voltage suppressors

The present invention discloses a combustor system and method of measuring impurities in the combustion system. The combustion system includes an up-stream fuel injection point; a down-stream turbine combustor; a flame zone in the turbine combustor comprising a plurality of axial sub-zones; an optical port assembly configured to obtain a non-axial, direct, optical view of at least one of the plurality of axial sub-zones, and an impurity detection system in optical communication with the optical port assembly.

Impurity detection in combustor systems

In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

Silicon-carbide MOSFET cell structure and method for forming same

An apparatus includes an article and a detector. The article includes a substrate, a faceted structure disposed on the substrate, and a sensor layer disposed on the faceted structure. The faceted structure is disposed on the substrate first surface and itself has a surface. The faceted structure surface has peripheral edge defining a diameter of the faceted structure surface. The sensor layer is disposed on the faceted structure surface. The sensor layer can react or can interact with a target species when the target species is sufficiently proximate to the sensor layer. The sensor layer responds to the reaction or to the interaction in a detectable manner. The detector detects a response to the reaction, or to the interaction, of the target species with the sensor layer.

Detection apparatus and associated method

Growing community of inventors

Niskayuna, NY, United States of America

Peter Micah Sandvik