Microsemi Semiconductor Ulc

Microchip Technology Inc.

Peter Meyer

Kamran Rahbar

Tariq Haddad

Drew Jenkins

A timing device includes an oven having a chamber, a crystal oscillator disposed in the chamber that generates a clock signal, and one or more sensors to generate operational characteristic signals indicative of respective operational characteristics of the crystal oscillator or the oven. The timing device includes a plurality of I/O connections and an IC device. The IC device includes processing logic to generate information that indicates how the generated clock signal is to be modified and a modulator coupled to the processing logic and the crystal oscillator. The modulator modulates the generated clock signal in relation to the information to generate a modulated clock signal indicative of the one or more operational characteristics of the crystal oscillator or the oven. The modulator outputs the modulated clock signal over a single one of the plurality of I/O connections.

Method and apparatus for conveying clock-related information from a timing device

A method for transferring first and second encoded client clock signals over a carrier clock domain between integrated circuits, including in a first integrated circuit encoding a phase change of the first client clock signal from a last recorded phase onto the carrier clock signal in first bit positions, encoding a phase change of the second client clock signal from a last recorded phase onto the carrier clock signal in second bit positions different from the first bit positions, and transmitting the carrier clock signal with the encoded phases of the first client clock signal and the second client clock signal over a single wire from the first integrated circuit to a second integrated circuit.

Circuits and methods for transferring two differentially encoded client clock domains over a third carrier clock domain between integrated circuits

A clock recovery device recovers a master clock over a packet network from incoming synchronization packets. A frequency locked loop generates a control input to a controlled oscillator, which generates an output clock. The frequency locked loop is responsive to pure offset information obtained from the incoming synchronization packets. A transient phase adjuster extracts information from the incoming synchronization packets taking into account transit delays to effect fast frequency adjustment of the control input and to provide a phase adjustment input to the frequency locked loop. A secondary phase path is selectable in response to de-activation of the transient phase adjuster to provide a phase correction to the control input derived from said pure offset information when the transient phase adjuster is inactive.

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Ottawa, Canada

Peter Meyer