Lsi Logic Corporation

Semiconductor Components Industries, LLC

Nantero, Inc.

Peter McGrath

Shiqun Gu

Derryl J Allman

Thomas Rueckes

Prasad Venkatraman

Richard Carter

Hong Lin

Masaichi Eda

Ryan Tadashi Fujimoto

James Elmer

Gordon M Grivna

Dean E Probst

Peter Austin Burke

Zia Hossain

Balaji Padmanabhan

Duane B Barber

Jeffery Allen Neuls

Jim Elmer

Shioun Gu

In one embodiment, a method of forming a semiconductor device forms gate trenches in a semiconductor substrate. A portion of the material between the trenches is narrowed and another material is formed on sidewalls of the narrowed portion that is substantially not etched by an etchant that etches the material of the portion of the material between the trenches. Source and gate contact openings are formed together.

Method of forming a semiconductor device

In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.

Method of making an insulated gate semiconductor device having a shield electrode structure

A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer). Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using C1, F plasma) the portions of the hard mask which have been already partially etched away.

Techniques for precision pattern transfer of carbon nanotubes from photo mask to wafers

A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer) Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using Cl, F plasma) the portions of the hard mask which have been already partially etched away.

An inventive semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semiconductor device and the field oxide. An etch stop layer is formed over the oxide layer. An inter layer dielectric layer is formed over the etch stop layer. At least one contact hole is etched through the inter layer dielectric layer, the etch stop layer and at least partially through the oxide layer. The contact hole is filled with a conductive material.

Semiconductor chip with borderless contact that avoids well leakage

Optical emission spectra from a test wafer during a plasma process are measured using a spectrometer. The plasma charging voltage retained by (detected by) the test wafer is measured after the process step is completed. The emission spectra are correlated with the plasma charging voltage to identify the species contributing to the plasma charging voltage. The optical emission spectra are monitored in real time to optimize the plasma process to prevent plasma charging damage. The optical emission spectra are also monitored to control the plasma process drift.

Method of reducing process plasma damage using optical spectroscopy

Method for preventing borderless contact to well leakage

A method of making a semiconductor device includes providing a first element formed of a first substantially electrically conductive material and having an upper surface. A second element adjacent to the first element is provided. The second element is formed of a first substantially non-electrically conductive material. An upper surface of the second element slopes downwardly toward the upper surface of the first element. A first layer of a second substantially non-electrically conductive material is disposed over the upper surface of the first element and the upper surface of the second element. The first layer has a thickness in the vertical direction that is greater in an area over the downward slope of the second element than in an area over the first element. An etching process is performed such that the layer is perforated above the upper surface of the first element and imperforated in the vertically thicker area above the downwardly sloping upper surface of the second element.

Method and apparatus for reducing microtrenching for borderless vias created in a dual damascene process

A dielectric film block is used in semiconductor processing to protect selected areas of the wafer from silicidation. The selected areas may include resistors. A first layer of oxide is formed on the resistor and a second layer comprising SiON or Si N is disposed on the oxide. A mask is patterned to allow etching to take place in the areas where silicide formation is desired. The oxide layer serves as an etch stop layer during etching of the second layer.

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Portland, OR, United States of America

Peter McGrath