Xilinx, Inc.

Peter Mccolgan

Tim Tuan

Juan J Noguera Serra

David Clarke

Zachary Dickman

Javier Cabezas Rodriguez

Amarnath Kasibhatla

Saurabh Mathur

Francisco Barat Quesada

An apparatus includes a data processing array having a plurality of array tiles. The plurality of array tiles include a plurality of compute tiles. The compute tiles include a core coupled to a random-access memory (RAM) in a same compute tile and to a RAM of at least one other compute tile. The data processing array is subdivided into a plurality of partitions. Each partition includes a plurality of array tiles including at least one of the plurality of compute tiles. The apparatus includes a plurality of clock gate circuits being programmable to selectively gate a clock signal provided to a respective one of the plurality of partitions.

Multiple partitions in a data processing array

Growing community of inventors

North Dublin, Ireland

Peter Mccolgan