Emulex Corporation

Emulex Design & Manufacturing Corporation

California Institute of Technology

Emulex Corporatioln

Peter Mark Fiacco

Bradley Eugene Roach

Vi Chau

Michael Yu Liu

Sam S Su

Vuong Cao Nguyen

Stuart B Berman

John Sui-kei Tang

Daming Jin

Wayne T Rickard

Greg Scherer

Sam Shan-Jan Su

Karl M Henson

David James Duckman

Shak Loong Kwok

Jennifer Sullivan

Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.

Restore PCIe transaction ID on the fly

Embodiments of the present invention are directed to systems and methods for controlling the temperature of an internal device while reducing or minimizing the involvement of the host. Thus, some of the heat monitoring and remediation work may be offloaded to the actual device itself. The device may monitor its own temperature and, in the event of high temperature, perform device specific heat reduction actions without involving the host. Furthermore, the device may, upon detecting temperature within a predefined range, alert the host of a high temperature condition in order to allow the host to perform temperature reduction measures. Also, the device may, upon detecting temperature within a predefined range, alert the host of an impending device shutdown and shut the device down. In addition, the device may periodically save its temperature into non-volatile memory in order to create a temperature log.

Chip overheating protection

A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Supercharge message exchanger

A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from atleast two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

A communication processor sends and receives frames of data and commands. Transmit and receive protocol engine is controlled by host driver software which utilizes predetermined bits to indicate which frame is the last frame in a series of frames. This information is then placed in the transmit frame before it is sent.

Communication processor having buffer list modifier control bits

A method and apparatus for processing and transferring frames of data in a computer data link that maps incoming frames to a specific buffer ring in host memory based on routing control and type fields in each frame. More particularly, a Fibre Channel link port contains receiver routing code (RRCode) registers that allow host software to set up routing control (R.sub.-- CTL) match and mask fields, and TYPE match and mask fields. The link port uses these registers to match and mask against corresponding R.sub.-- CTL/TYPE fields in a received frame to determine which of several R.sub.-- CTL/TYPE host memory buffer rings should be used to store the received frame. The link port places a code (RRCode) in a start of frame (SOF) status word associated with a frame. The RRCode indicates a specific R.sub.-- CTL/TYPE host memory buffer ring, or indicates that no match was found or that multiple matches were found. A protocol engine reads the RRCode field in the SOF status word of the received frame, and queues a direct memory access (DMA) operation to an appropriate R.sub.-- CTL/TYPE buffer ring. The host may then process the contents of the indicated buffer ring. Since the buffer rings are 'pre-sorted' as to frame type, the host may more efficiently respond to incoming frames.

Method of mapping fibre channel frames based on control and type header

A system is configured to provide an efficient management or control of a buffer memory system. The system can also be used to transmit data between communicating components of a computer system. A first-in-first-out memory stores a list of buffer pointers, and control logic returns buffer pointers from the transmit registers, and moves buffer pointers to the bottom of the FIFO memory.

Efficient transmission buffer management system

A full duplex communication processor simultaneously sends and receives frames of data and commands. Separate transmit and receive protocol engines are controlled by separate sequencers. This enables frames of data to be received and transmitted simultaneously without involving a host CPU on a frame-by-frame basis.

Full-duplex communication processor which can be used for fibre channel

A partitioned memory is divided into a number of large buffers, and one or more of the large buffers is divided to create an equal number of small buffers. Each remaining large buffer is associated with one small buffer, and the paired buffers may be addressed by a single pointer. The pointers are stored in a first-in-first-out unit to create a pool of available buffer pairs.

Memory buffer system using a single pointer to reference multiple

A method and apparatus for linking two independent caches which have related information stored therein. Each unit of information stored in a first cache memory is associated with one unit of information stored in the second cache memory. Each unit of information stored in the first cache memory includes a pointer or index to the associated information unit in the second cache memory. Each information unit stored in the second cache is only stored once, regardless of the number of units in the first cache that are associated with a particular unit within the second cache. Therefore, even if more than one unit of information within the first cache memory is associated with the same unit of information within the second cache memory, that unit of information stored in the second cache memory is only stored once.

Linked caches memory for storing units of information

A method and apparatus for establishing a large number of EDTOV timers, each determining when an event has failed to occur on an exchange of a communications protocol. Values for each timer are maintained as a timer array. The entire timer array is read at regular scan intervals by a state machine and decremented by four associated hardware decrementers, four timers at one time. A Scan Interval variable determines the scan interval. The present invention is capable of scan intervals of up to 100 ns. Active time values are read, checked for zero, decremented preferably by one, and written back to the timer array. If a timer is detected as having timed out (equal to zero), then a value which identifies the exchange associated with that timer is logged into a time-out FIFO and 'FF'h is written back into the timer. At the heart of the invention is the efficient use of dedicated hardware to decrement or otherwise alter the values of each timer as appropriate, and the use of a dedicated state machine to read values for each timer, provide the value to the hardware, and then load the new value of each timer back into memory.

Growing community of inventors

Costa Mesa, CA, United States of America

Peter Mark Fiacco