International Business Machines Corporation

Peter M Smith

David C Conway-Jones

David J Brown

Kelvin Wong

Michael John Palmer

Thomas W Rickard

Jong-Han Kim

In one embodiment, a method for back-up of data to flash memory is provided. Backed up data is organized into one or more stripes, wherein a stripe comprises a set of pages across all available flash memory devices which have a same block and page address. Responsive to encountering an error in a block of flash memory during back-up of a particular stripe of data, the particular stripe of data is rewritten starting at a next available page address and excluding a page of flash memory for the block having the error. Subsequent stripes of data in the block having the error are written to pages excluding the page of flash memory for the block having the error.

Back-up and restoration of data between volatile and flash memory

This specification concerns signal processing apparatus for processing line synchronization pulses in a line synchronization signal that define an analog video signal line period. The apparatus comprises a phase locked loop (40) for generating a clock signal of a frequency that is a multiple of the line synchronization signal frequency. The phase locked loop (40) comprises a counter (100) for dividing the clock signal by said multiple. The apparatus further comprises logic (110,50) for resetting the counter (100) upon detection of a spurious pulse introducing a time interval into the line synchronization signal of less than the line period of the video signal. The apparatus is particularly useful in image processing systems for digitizing analog video signals that have been replayed via a conventional, domestic video tape player, and therefore may comprise spurious line sync pulses introduced by playback head skip.

Signal processing apparatus

A controller for a first in first out (FIFO) memory comprises detector logic for detecting any difference between the number of addresses in the memory into which data is written and the number of addresses in the memory from which data is read. Comparator logic connected to the detector logic generates a request data transfer signal in response to said difference becoming greater than or equal to a threshold. Threshold select logic connected to the comparator logic is responsive to data having first and second portions being written to the memory. The threshold select logic sets the threshold to a first value when the first portion is being written and sets the threshold to a second value, greater than the first value, when the second portion is being written. Because different thresholds are assoicated with the portions, data, such as a digitized video signal having active line portions separated by control portions for example, can be transferred via the FIFO from one system to another more efficiently in terms of communication bandwidth usage.

FIFO memory controller for a digital video communications channel having

Signal processing apparatus comprises a chrominance subsampler (10) for sampling the U and V components of a video signal in response to an enable signal. A counter (30) responsive to the horizontal synchronization component of the video signal generates the enable signal upon detection of a predetermined number of horizontal synchronization pulses. Logic (60,70,80) responsive to the vertical synchronization component of the video signal resets and disables the counter (30) upon detection of a vertical synchronization pulse. Logic (50,60,70,80) restarts the counter (30) from a reset state upon detection of a predetermined polarity in the V component of the video signal.

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Winchester, United Kingdom

Peter M Smith