Itt Industries, Inc.

Deutsche Itt Industries Gmbh

Etutsche Itt Industries Gmbh

Peter M Flamm

Soenke Mehrgardt

Leslie Miskin

Martin Winterer

Laurin C Freyberger

Friedrich Schmidtpott

Ljubomir Micic

Heinrich Pfeifer

Daniel Mlynek

Hans-Juergen Desor

Thomas Fischer

Alfred Praxmarer

Rolf Deubert

A digital phase-locked loop has a periodically overflowing digital oscillator (DCO), implemented as a modulo adder, and a processor device. The processor device adjusts the period T of the digital oscillator to a nominal period, determined from periodically occurring synchronizing pulses, by comparing the actual phase of the digital oscillator with a set phase at the control clock rate of the periodic synchronizing pulses. After the digital oscillator has been locked to the nominal period, the processor device compares the phases by using a double-frequency signal sequence of one-half line period derived from the digital oscillator output signal. The DCO output signal is fed to a correction device where an address-phase signal, locked to the DCO output signal, is generated so that when a non-periodic synchronizing pulse occurs, the address-phase signal is shifted by one period of the signal sequence of one-half line period with respect to the digital oscillator output signal.

Digital phase-locked loop

Line flicker is detected by comparing luminance values provided by a video signal in vertically successive lines of two temporally successive fields. If there is a step change in adjacent lines, indicative of line flicker, the line flicker is corrected by adaptively delaying or accelerating corresponding lines within the field that experienced the step change.

Apparatus and method for reducing line flicker in a television picture

A digital limiter for processing a digital video signal includes a limiter stage whose output is subtracted from the input to the stage in a subtracting stage. The resulting difference signal is accumulated by means of an accumulating device. The accumulated signal is added to the digital video signal to be processed. The accumulator provides a memory function for the signal component clipped in the limiter. It also includes a leakage device, so that the accumulated signal can decrease again after the start of limiting action.

Apparatus and method for limiting digital video signals

A remote control system, particularly for television sets, includes a remote control receiver and a remote control transmitter. The receiver and transmitter are switched to the menu mode by means of a menu key. At least two menu fields are associated with the remote control receiver and are displayed on the screen of the television set. The menu fields are individually selectable by means of the remote control transmitter. The selection is preferably accomplished by manually aligning the remote control transmitter with the displayed menu field to be selected.

Remote control system with menu driven function selection

A digital color-signal-processing circuit generates a phase-angle signal and a magnitude signal as outputs in response to an R-Y color-difference signal and a B-Y color-difference signal. The circuit includes a resolver which convertes cartesian coordinate representations of the color-difference signals into polar coordinate representations of the phase-angle signal and the magnitude signal. The phase-angle signal carries the hue information, which is processed in a hue stage. The magnitude signal carries the saturation information, which is processed in a saturation stage. The processed phase-angle signal and the processed magnitude signal are reconverted to cartesian coordinate representations of the R-Y and B-Y color-difference signals in a reconverting resolver.

Digital color-signal-processing circuit that provides independent

In a chroma control circuit for a digital television receiver, the system clock lies in the range of four-times the chrominance-subcarrier frequency. The originally received color-burst signal is locked in frequency and phase to the system clock by means of an all-digital phase-locked loop. The phase-difference angle between the color-burst signal and the system clock appears as a sine or cosine value in the two standard color-difference signals of the chrominance demodulator during the reception of the color-burst signal. One of the standard color-difference signals, the B-Y signal, is fed through a horizontal-frequency-suppressing loop filter to a digital oscillator. The latter determines the speed of rotation of a hue adjustment angle rotating at approximately constant angular speed. The respective sine and cosine values of the hue adjustment angle are read as data values from first and second read-only memories, respectively, and are fed to the sine and cosine inputs of a hue adjuster in a calculating stage which derives the color-burst signal and the chrominance signal.

Chroma control circuit for a digital television receiver

To raise the integration level of a video recorder, and to provide a uniform circuit concept suitable for all three color-television standard (PAL, NTSC, SECAM) which, in particular, requires only slight modifications for adaptation to the respective standard, signal processing is performed by fast digital circuits whose signals are stored on the recording medium not in digital form, but after digital-to-analog conversion. The composite color signal is converted into digital form by a fast analog-to-digital converter (aw) whose sampling signal (fc) has a fixed frequency (Fc) for all three color-television standards. Digital signal processing in the chroma channel is performed at a fixed subcarrier frequency (zt) for all three color-television standards which is an integral subharmonic of the sampling frequency (Fc).

Video recorder with a magnetic recording medium in the form of a tape

This circuit arrangement is designed for use in digital color-television receivers or the like and contains for each of the two digital color-difference signals a slope detector to which both a digital signal defining an amplitude threshold value and a digital signal defining a time threshold value are applied. At least one intermediate value occurring during an edge to be steepened is stored, and at the same time value of the steepened edge, it is 'inserted' into the latter. This is done by means of memories switches, output registers, and a sequence controller.

Digital circuit for steepening color-signal transitions

From the digital color-difference signals (b-y, r-y), the digital flesh-tone correction circuit forms a signal corresponding to the tangent between the two color-difference signals by means of absolute-value stages, a comparator, an intermediate switch, and a divider. In a correction stage, this signal is changed into the address signal for a read-only memory which holds the sine and cosine values of a preset function within a presettable angle correction range. By suitably multiplying the sine and cosine values by the color-difference signals in a multiplier, the flesh-tone-corrected color-difference signals are produced.

Flesh tone correction circuit

A digital circuit is described for the clocked suppression of changes in a multidigit, positive or negative digital signal which have signs opposite to those of signal changes at previous instants of a clock signal.

Digital circuit for suppressing changes in a digital signal

For the dynamic compensation of the offset voltage in such converters each non-inverting comparator input (+) is connected via a first transfer transistor (T11, T12, T1p) to the signal input (SE) and via a second transfer transistor (T21, T22, T2p) to the associated voltage divider tap of the voltage divider as applied to the reference voltage (Ur). Moreover, each inverting comparator input (-), via a capacitor (C1, C2, Cp) is applied to the associated voltage divider tap and, via a third transfer transistor (T31, T32, T3p) and across a resistor (R'1, R'2, R'p) arranged in series therewith, to the associated comparator output. The second and third transfer transistors are rendered conductive during short intervals (T) between conversions by the clock signal (F), and the first transfer transistors are rendered non-conductive via the inverter (IV), and during the conversion time (t) the first transfer transistors are rendered conductive, and the second and third transfer transistors are rendered non-conductive. In television receivers, such MOS parallel A/D converters are suitable for processing the video signal, in which case the line sweep period serves as the conversion time (t), and the line fly-back period serves as the interval (T) between conversions.

MOS Parallel A/D converter

An improved digital integrated chrominance-channel circuit having gain control for color-television receivers includes at least one integrated circuit for digitally processing the composite color signal. The circuit includes a first limiter inserted between a parallel multiplier and a burst-amplitude-measuring stage, and a control stage including a parallel subtracter whose minuend input is fed with a reference signal, and whose subtrahend input is connected to the output of the burst-amplitude-measuring stage. A digital accumulator whose enable input is presented with a signal derived from the trailing edge of a burst gating signal is used as an integrator.

Digital integrated chrominance-channel circuit with gain control

To digitally synchronize the chrominance-subcarrier oscillator in the form of a phase-locked loop with the color burst contained in the composite color signal, suitable digital subcircuits are provided. During the keying pulse, the digital R-Y and B-Y color-difference signals are accumulated line by line. The corresponding R-Y value is then added to a desired phase value or a tint-control value, and for deviations from the burst phase between +90.degree. and -90.degree., the sum signal, after being limited if necessary, is applied to a digital-to-analog converter, filtered in a low-pass filter, and then used to control the chrominance-subcarrier oscillator. If the phase deviations lie between +90.degree. and +180.degree. or -90.degree. and -180.degree., the digital-to-analog converter is constantly fed with the upper or the lower limit value, respectively, via a switching stage. The latter has three switch positions, one for direct transfer and one for each of the two limit values, with the sign bit of the accumulated R-Y or B-Y value effecting the appropriate selection.

Color-television receiver with at least one digital integrated circuit

The color television receiver includes a square-wave clock generator used as a chrominance subcarrier oscillator generating at least four clock signals, the first of which has a frequency four times the chrominance subcarrier frequency, and the second to fourth of which have a frequency equal to the chrominance subcarrier frequency, the first and second clock signals having a mark/space ratio of 1:1; a stage providing a digital chrominance signal, a first digital circuit having as one input signal the digital chrominance signal, and as another input signal the digital chroma control signal to provide a digital amplitude control of the received chrominance subcarrier wave; and a second digital circuit to provide digital identification and color killer action and, if necessary, digital noise-dependent color killer action.

For the dynamic compensation of the offset voltage in such converters each non-inverting comparator input (+) is connected via a first transfer transistor (T11, T12, T1p) to the signal input (SE) and via a second transfer transistor (T21, T22, T2p) to the associated voltage divider tap of the voltage divider as applied to the reference voltage (Ur). Moreover, each inverting comparator input (-), via capacitor (C1, C2, Cp) is applied to the associated voltage divider tap and, via a third transfer transistor (T31, T32, T3p) and across a resistor (R'1, R'2, R'p) arranged in series therewith, to the associated comparator output. The second and third transfer transistors are rendered conductive during short intervals (T) between conversions by the clock signal (F), and the first transfer transistors are rendered non-conductive via the inverter (IV), and during the conversion time (t) the first transfer transistors are rendered conductive, and the second and third transfer transistors are rendered non-conductive. In television receivers, such MOS parallel A/D converters are suitable for processing the video signal, in which case the line sweep period serves as the conversion time (t), and the line fly-back period serves as the interval (T) between conversions.

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Freiburg, Germany

Peter M Flamm