Virginia Tech Intellectual Properties, Inc.

Intransa, Inc.

Macaulay-brown, Inc.

Peter M Athanas

Cameron D Patterson

Jonathan Peter Graf

Paul D McFall

Joshua Nathaniel Edmison

Ray A Bittner, Jr

Timothy G Dunham

Justin D Rice

Anthony Mahar

Matthew T Shelburne

Jorge A Suris Pletri

Benjamin J Muzal

Henry J Green

John K Bowen

Tom B Brooks

Mark T Jones

Barry L Polakowski

Kevin J Paar

A hardware-facilitated secure software execution environment provides protection of both program instructions and data against unauthorized access and/or execution to maintain confidentiality and integrity of the software or the data during distribution, in external memories, and during execution. The secure computing environment is achieved by using a hardware-based security method and apparatus to provide protection against software privacy and tampering. A Harvard architecture CPU core is instantiated on the same silicon chip along with encryption management unit (EMU) circuitry and secure key management unit (SKU) circuitry. Credential information acquired from one or more sources is combined by the SKU circuitry to generate one or more security keys provided to the EMU for use in decrypting encrypted program instructions and/or data that is obtained from a non-secure, off-chip source such as an external RAM, an information storage device or other network source. In a non-limiting illustrative example implementation, the EMU decrypts a single memory page of encrypted instructions or data per a corresponding encryption key provided by the SKU. Although instantiated on the same chip, the CPU core does not have direct access to the SKU circuitry or to encryption key information generated by the SKU.

Hardware-facilitated secure software execution environment

A method, and system, for reconfiguring an FPGA which has a static region and a dynamic region is provided. The method includes the steps of: (a) providing a dynamic module library having information of predetermined modules; (b) receiving a reconfiguration request external to the FPGA; (c) computing reconfiguration of the FPGA at a predetermined location using predetermined module information from the dynamic module library and the reconfiguration request, and generating reconfigurable partial bitstreams; and (d) sending partial bitstreams from the predetermined location to the FPGA to perform the reconfiguration.

Wires on demand: run-time communication synthesis for reconfigurable computing

A data storage system includes memory, a controller, and an Ethernet interface enabling sending and/or receiving Ethernet packets to or from a client system, according to a first protocol. The controller is coupled between the memory and the Ethernet interface and essentially carries out a translation function. Information packets from the client system are translated from a first protocol to a second protocol for use by the memory, and information from the memory is translated from the second protocol to the first protocol for use by the client system as Ethernet packets.

Method and apparatus for accessing memory using Ethernet packets

The present invention provides a controller system including a common controller, a first interface, a second interface, and an adapter. The first interface is used to receive and to send data according to a first protocol having a format useable by a computer system. The common controller is coupled between the first interface and the second interface to translate between the first protocol and the second protocol, the second protocol is used by a memory coupled to the common controller. The second interface is used to store and to retrieve data from the memory according to the second protocol. The adapter function can be coupled between the memory and the common controller. The memory forms a response to a request by the computer system, with the response including at least one of (A) storing information, (B) retrieving information, and (C) providing status information.

Method and apparatus for a controller capable of supporting multiple protocols

Higher performance is gained through a new architecture which implements a new method of computational resource allocation, utilization and programming based on the concept of Worm-hole Run-Time Reconfiguration (RTR). A stream-driven Worm-hole RTR methodology extends contemporary data-flow paradigms to utilize the dynamic creation of operators and pathways, based upon stream processing in which parcels of data move through custom created pathways and interact with other parcels to achieve the desired computation. These parcels independently allocate the necessary computing resources and data paths as they navigate through the platform. The Worm-hole RTR platform consists of a large number of configurable functional units that perform the custom computations and rich, configurable interconnection pathways between the functional units. Once a computational pathway has been established (sensitized) by the head of the stream parcel, data are processed through the pathway with zero overhead. All ports entering the computing platform serve both to configure operations and pathways and to pass computational data streams. As a result, programming and configuration is not limited to a single port. Configuration through multiple independent ports allows greater concurrency, faster reconfiguration, and fewer computational dependencies, all with relatively low cost in silicon.

Worm-hole run-time reconfigurable processor field programmable gate

Growing community of inventors

Newport, VA, United States of America

Peter M Athanas