Rockwell International Corporation

University of California

Other

Hughes Aircraft Company

Lawrence Livermore National Security, LLC

Newport Fab, LLC

Coldwatt, Inc.

Socal Simulations, LLC

Peter M Asbeck

Mau-Chung Frank Chang

David L Miller

Peter J Zampardi

Lawrence E Larson

Ian Galton

Richard L Pierson, Jr

Mau Chung Chang

Seyed Bagher Rabet

Klaus Florian Schuegraf

Charles E Chang

Lars F Voss

Adam M Conway

Berinder P S Brar

Xiaozhong Dang

Richard C Edwards

Keh-Chung Wang

Julia J Brown

Donald Kimball

Victor V Khitrov

Paul Kempf

Tammy Chang

Lingquan Wang

Benjamin J Fasenfest

Garth D Hammond

Narek Rostomyan

Mingyuan Li

Sravya Alluri

Charles W Tu

Jinseong Jeong

Kazuhiro Mochizuki

Rebecca Welty

Silvanus S Lau

Paul Theilmann

Edward T Yu

Dale W Penner

Adaptive bias networks include small transistors connected to adjust gate bias voltage of one or more transistors of an amplifier or amplifier stage, or in a main or auxiliary path of a compound amplifier such as a Doherty amplifier. The small transistors are sized to avoid additional loading of the input. The adaptive bias circuits of preferred embodiments adjust the gate bias to produce a boost in gate bias voltage of an nFET transistor when the input power is in an upper portion of the amplifier or amplifier stage's input power range, thereby increasing the gain, and reduce gate bias voltage of a pFET transistor in the upper portion of the amplifier's input power range, thereby also increasing the gain. The adaptive bias networks can be implemented with varactors to vary DC voltage across the varactor to change its capacitance and compensate changing input capacitance of the amplifier input FET.

Adaptive bias circuits and methods for CMOS millimeter-wave power amplifiers

A method for power amplification uses circuitry including a main amplifier and an auxiliary amplifier that are constructed and operate such that an input is applied to the main and auxiliary amplifiers via an input network. At low power levels, the auxiliary amplifier is off and the main amplifier sees a large impedance. At maximum power level, both the auxiliary and main amplifiers operate at full power and there is a constant phase shift between them. While transitioning from low to maximum power, systematic AM-AM and AM-PM variations generated due to the phase shift provided by the input network, bias differences between the main and auxiliary amplifiers, and nature of the output combiner to compensate device related distortions.

Method for enhancing power amplifier efficiency and linearity and power amplifier

Power amplifier apparatuses and techniques for optimizing the design of power amplifiers are disclosed. In one aspect, a method for optimizing a power amplifier includes selecting a circuit topology for the power amplifier. The circuit topology includes one or more photoconductive switches and an impedance matching network including one or more parameter values representative of the impedance matching network or the photoconductive switches that can be adjusted. The method further includes selecting one or more optimization goals for the impedance matching network and the one or more photoconductive switches, and adjusting the one or more parameter values according to the one or more optimization goals. The one or more optimization goals include an efficiency at a particular power output.

High efficiency photoconductive semiconductor switch-based amplifier for high power microwave transmission

Embodiments of the present invention provide cross-coupled rectifiers that use near zero-threshold transistors in a switching topology, but provide a topology that avoids reverse conduction problems. Importantly, preferred embodiment rectifiers of the invention only provide a slightly increased on-resistance in each branch, while providing both very high operating efficiency and very low turn-on voltage. An embodiment of the invention is a voltage rectifier for the conversion of RF energy into DC voltage with a turn-on threshold voltages approaching 0V.

Switch mode voltage rectifier, RF energy conversion and wireless power supplies

An embodiment of the invention is a method of generating a reduced bandwidth envelope signal V(t) for the power supply modulator of an RF amplifier. An envelope signal of an RF amplifier input V(t) is low pass filtered. The filtered envelope signal is subtracted from the envelope signal to obtain a difference signal, which is rectified to produce a residue signal. The residue signal is low pass filtered and added back into the filtered envelope signal. An iterative process of the rectifying, low pass filtering the residue signal adding it back is continued until a condition of V(t)&#x2267;V(t) is met. Another embodiment provides a method of generating a reduced bandwidth envelope signal V(t) for the power supply modulator of an RF amplifier. An envelope signal of an RF amplifier input V(t) is low pass filtered. The filtered envelope signal is subtracted from the envelope signal to obtain a difference signal, which is rectified to produce a residue signal. The residue signal is low pass filtered and multiplied by a first constant that is greater than one, and then added back into the filtered envelope signal. A second constant is added into the filtered envelope signal so that the condition V(t)&#x2267;V(t) is met.

Supply-modulated RF power amplifier and RF amplification methods

The invention provides a transistor having a substrate, a structure supported by the substrate including a source, drain, gate, and channel, wherein the source and the channel are made of different materials, and a tunnel junction formed between the source and the channel, whereby the tunnel junction is configured for injecting carriers from the source to the channel.

Low voltage transistors

The invention is directed to digital generation of RF signals. In the digital domain, digital RF signals are converted to the digital signals clocked at a high speed clock that is phase-synchronized with the RF carrier. A band-pass delta-sigma modulator produces a bit stream from the converted digital signals.

Radio transmission frequency digital signal generation

The invention provides methods and devices for estimating power amplifier nonlinearity using simple correlation techniques. Methods and devices of the invention can monitor a power amplifier that has digitally modulated inputs and an output containing more than one signal stream. A preferred method of the invention creates a test signal by forming the products of several pseudorandom noise sequences from the digitally modulated inputs to the power amplifier. Nonlinear contributions of the power amplifier output are determined by cross-correlating the test signal and the total output signal of the power amplifier. In preferred embodiments, the determined nonlinear contributions of the power amplifier are used to introduce corrective predistortion in the power amplifier.

Correlation method for monitoring power amplifier

A substrate driven field effect transistor (FET) and a method of forming the same. In one embodiment, the substrate driven FET includes a substrate having a source contact covering a substantial portion of a bottom surface thereof and a lateral channel above the substrate. The substrate driven FET also includes a drain contact above the lateral channel. The substrate driven FET still further includes a source interconnect that connects the lateral channel to the substrate operable to provide a low resistance coupling between the source contact and the lateral channel.

Substrate driven field-effect transistor

An improved HBT of the invention reduces the current blocking effect at the base-collector interface. Nitrogen is incorporated at the base-collector interface in an amount sufficient to reduce the conduction band energy of the collector at the base-collector interface to equal the conduction band energy of the base. In a preferred embodiment, a nitrogen concentration on the order of 2% is used in a thin &tilde;20 nm layer at the base-collector interface. Preferred embodiment HBTs of the invention include both GaAs HBTs and InP transistors in various layer structures, e.g., single and double heterojunction bipolar transistors and blocked hole bipolar transistors.

HBT with nitrogen-containing current blocking base collector interface and method for current blocking

A GaN-based HFET includes a set of layers all having a common face polarity, i.e., all being either Ga-face or N-face. One of the layers is a thin barrier layer having a first face with a positive charge and a second face with a negative charge thereby causing a potential change to occur between the two faces. The if potential change causes the barrier layer to prevent electron flow from a channel layer into a buffer layer. The GaN-based HFET may also be fabricated without a top barrier layer to obtain an inverted GaN-based HFET.

Gallium nitride-based HFET and a method for fabricating a gallium nitride-based HFET

A compound collector double heterojunction bipolar transistor (CCHBT) incorporates a collector comprising two layers: a wide bandgap collector region (e.g., GaAs), and a narrow bandgap collector region (e.g., InGaP). The higher electric field is supported in the wide bandgap region, thereby increasing breakdown voltage and reducing offset voltage. At the same time, the use of wide bandgap material in the depleted portion of the collector, and a higher mobility material toward the end and outside of the depletion region, reduces series resistance as well as knee voltage.

Methods and apparatus for a composite collector double heterojunction bipolar transistor

In one disclosed embodiment, a collector is deposited and a base is grown on the collector, for example, by epitaxially depositing either silicon or silicon-germanium. An emitter is fabricated on the base followed by implant doping an extrinsic base region. For example, the extrinsic base region can be implant doped using boron. The extrinsic base region doping diffuses out during subsequent thermal processing steps in chip fabrication, creating an out diffusion region in the device, which can adversely affect various operating characteristics, such as parasitic capacitance and linearity. The out diffusion is controlled by counter doping the out diffusion region. For example, the counter doped region can be implant doped using arsenic or phosphorous. Also, for example, the counter doped region can be formed using tilt implanting or, alternatively, by implant doping the counter doped region and forming a spacer on the base prior to implanting the extrinsic base region.

High performance bipolar transistor

A hybrid power transistor (40) includes a vertical PNP bipolar transistor (42) having a floating base (46). A junction-gate type field-effect transistor (FET) (62) has a lateral N-type channel (64,66) and a vertical electron injection path (54) from the channel (64,66) into the base (46) of the bipolar transistor (42). The FET channel current and thereby the electron injection current are controlled by the FET gate voltage. The injection current conductivity modulates the base (46) and thereby controls the collector current of the bipolar transistor (42). The FET (62) may have a high electron mobility transistor (HEMT), junction-gate field-effect transistor (JFET) or metal-semiconductor field-effect transistor (MESFET) structure. The FET (62) does not require a gate insulating layer, enabling fabrication of the hybrid transistor (40) in the group III-V material system.

Hybrid bipolar/field-effect power transistor in group III-V material

A variety of embodiments of varactor diodes are disclosed ranging from an N.times.N matrix assembly of individually packaged diodes arranged in N rows and columns to a multi-continuous layered varactor. The matrix assembly varactor has N rows of discrete devices electrically coupled in parallel and multiple rows vertically aligned and electrically coupled in series to each other. The overall matrix assembly capacitance equals the individual diode capacitance of such assembly. When used as a tuning component across a tank coil transmission line, the RF voltage across any device in the matrix assembly is equal to the tank voltage divided by N.

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San Diego, CA, United States of America

Peter M Asbeck