Freescale Semiconductor,inc.

Nxp Usa, Inc.

Peter Limmer

Michael Rohleder

Stefan Doll

Dirk Moeller

Clemens Alfred Roettgermann

A bit storage device, integrated circuit, and method are provided. The bit storage device comprises registers to store an actual value, an inverse value, a differential actual value, and a differential inverse value, a validation circuit including validation inputs coupled to outputs of the registers and including a validity output to provide a validity indication, and a write circuit including write circuit inputs coupled to the registers, the write circuit configured to cause, at a first clock edge, the first register to store the actual value and either the second register to store the inverse value or the fourth register to store the differential inverse value, and, at a second clock edge, the third register to store the differential actual value and the other of the second register and the fourth register to store to store the inverse value or the differential inverse value, respectively.

Safe secure bit storage with validation

A system-on-chip comprising a sender unit and a receiver unit and a method of operating thereof are described. The sender unit comprises a send counter for providing a send counter value. The receiver unit comprises a receive counter for providing a receive counter value. The sender unit is arranged to increment the send counter value by an increment and send a data packet to the receiver unit. The receiver unit is arranged to receive the data packet and increment the receive counter value by the increment. In a challenge operation, the sender unit sends the send counter value to the receiver unit. In a challenge response operation, the receiver unit receives the send counter value, compares the values, and generates a comparison result. Loss of data packets from the sender unit as well as reception of unexpected data packets from a third functional unit may thus be detected.

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Munich, Germany

Peter Limmer