Advanced Micro Devices Corporation

Citizen Finetech Miyota Co., Ltd

Peter Lapidus

Yat-Loong To

Ronald Hathcock

David B Hollenbeck

David Larsen

Apparatus and methods are disclosed that can provide for voltage translation and conversion that can be applied, as an example, in a microdisplay including a plurality of pixels that are driven at a pixel drive voltage. A pixel is configured to receive a lower pixel drive voltage for one state of the pixel and an upper pixel drive voltage for an opposite state of the pixel. A memory circuit selectively couples the pixel to the lower voltage and the upper pixel drive voltage in response to control signals operable between the lower voltage and an intermediate voltage level that is less than the upper pixel drive voltage.

Voltage conversion apparatus suitable for a pixel driver and methods

A processing system comprising: i) a read-only memory (ROM) that stores original ROM code; ii) a custom array that stores replacement ROM code; and iii) control logic that receives an incoming ROM address and a read request signal generated by a source device. The control logic, in response to receipt of the incoming ROM address and the read request signal, compares the incoming ROM address to a patched address associated with the ROM. If a match occurs, the control logic outputs to the custom array a translated address associated with the patched address. The custom array then outputs a first line of replacement ROM code associated with the translated address.

Bypass custom array and related method for implementing ROM fixes in a data processor

There is disclosed, for use in an integrated circuit, an apparatus for driving a signal line in the integrated circuit. The apparatus comprises: 1) a line driver for receiving an incoming data signal and transmitting an outgoing data signal on the signal line; 2) a power source for supplying a plurality of power voltage levels to a power supply rail of the line driver; and 3) a power level controller for determining a data rate of the outgoing data signal and in response to the determination, selectively applying one of the plurality of power voltage levels to the power supply rail of the line driver to thereby modify an amplitude of the outgoing data signal.

Integrated circuit having programmable voltage level line drivers and method of operation

A flip flop includes a master portion operable to latch at least one of an input signal and an inverted input signal. The flip flop also includes a slave portion operable to latch at least one of the signal latched by the master portion and an inverted signal latched by the master portion in response to a first phase of a clock signal. The slave portion is also operable to be reset in response to a second phase of the clock signal.

Flip flop supporting glitchless operation on a one-hot bus and method

A method for providing a shared write driver is provided. The method includes providing a write driver for a memory array. The memory array comprises a plurality of memory columns. The write driver is coupled to the plurality of memory columns.

Method and system for providing a shared write driver

A method for providing a low power memory array is provided. The method includes partitioning a memory array into at least two memory sections. Each memory section comprises a plurality of memory cells. A sense amplifier is provided for the memory sections. An operation request for a specified memory cell in one of the memory sections is received. The memory section comprising the specified memory cell is accessed. The requested operation is performed on the specified memory cell.

Method and system for providing a low power memory array

There is disclosed a reduced noise line driver for driving a signal line in an integrated circuit. The reduced-noise line driver comprises: 1) an N-type transistor having a source coupled to ground and a drain coupled to the signal line; 2) a P-type transistor having a source coupled to a power supply rail and a drain coupled to the signal line; 3) a first controller having an input for receiving an incoming signal and an output coupled to a gate of the N-type transistor; and 4) a second controller having an input for receiving the incoming signal and an output coupled to a gate of the P-type transistor, wherein the first controller and the second controller selectively switch the N-type transistor and the P-type transistor ON and OFF such that the N-type transistor and the P-type transistor are never ON simultaneously.

Growing community of inventors

Boulder, CO, United States of America

Peter Lapidus