Infineon Technologies Ag

Qimonda Ag

Infineon Technologies Aktientgesellschaft

Peter Lahnor

Alexander William Simpson

Stephan Wege

Olaf Kuehn

Andreas Roemer

Peter Baars

Roland Thewes

Wolfgang Roesner

Martin Kerber

Hans-Peter Moll

Gerhard Enders

Martin Popp

Klaus Muemmler

Peter Moll

Michael Beck

Stefan Jakschik

Werner Graf

Bernd Hintze

Lars Heineck

Arnd Scholz

Odo Wunnicke

Andreas Orth

Mark Hollatz

Johannes Heitmann

Andrei Josiek

Gouri Sankar Kar

One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Interconnect structure for semiconductor devices

In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.

Method and apparatus for reducing charge trapping in high-k dielectric material

A method for forming an integrated circuit having openings in a mold layer and for producing capacitors is disclosed. In one embodiment, nanotubes or nanowires are grown vertically on a horizontal substrate surface. The nanotubes or nanowires serve as a template for forming openings in a mold layer. The substrate is covered with a mold material after the formation of the nanowires or nanotubes. One embodiment provides mold layers having openings with a much higher aspect ratio.

Methods for forming an integrated circuit, including openings in a mold layer from nanowires or nanotubes

A method of determining the endpoint of a planarizing process is disclosed. An endpoint detection signal is selectively sampled from at least one predetermined location within a planarizing region defined on a planarizing web. Planarization is stopped when the endpoint criterion based on the endpoint detection signal is detected.

Method of determining the endpoint of a planarization process

A process for planarizing a process layer having structures and has been applied to a working surface of a semiconductor device, includes abrading the process layer down to the working surface using a polishing device. The working surface is planarized, and a defect density in the working surface is minimized and the polishing process is topology-independent.

Defect-minimizing, topology-independent planarization of process surfaces in semiconductor devices

A method and apparatus of planarizing substrates is disclosed. A planarizing web medium is prepared for planarizing substrates to reduce defect generation. The planarizing web has a planarizing region and preparing region defined thereon, wherein at least one portion of the preparing region is outside the planarizing region. The web medium is advanced to move one portion of the web out of the planarizing region and another portion into the planarizing region.

Method of planarizing substrates

The optimization of a CMP process provides the use of an auxiliary layer ( ) between a dielectric ( ) in the vicinity of patterned portions and a layer of a liner ( ). If the liner ( ) is perforated in the CMP process, then the undercutting of the liner ( ) by the chemical removal of the auxiliary layer ( ) simplifies the process overall. Advantages are significantly lower defect densities due to CMP scratches, fewer short circuits, fewer alignment errors.

CMP process

A method and a semiconductor wafer configuration for producing an alignment mark for semiconductor wafers. In the method, an alignment mark region surrounded by a metal frame is formed on the semiconductor wafer. Subsequently, the alignment mark region and the metal frame are completely buried in at least one dielectric layer, in order to define an alignment mark area in the alignment mark region on the dielectric layer with a photolithography process. The boundary of the alignment mark area lies at a uniform distance within the boundary of the alignment mark region, defined by the metal frame. Subsequently (to uncover the alignment mark area by an anisotropic etching of the dielectric layer), the etching depth is defined in such a way that the alignment mark opening extends at least as far as the level of the metal frame.

Method and semiconductor wafer configuration for producing an alignment mark for semiconductor wafers

A substrate holder is described which has a movable plate elastically mounted inside a main body. With the substrate holder, a polishing operation can be performed in two basic operation modes corresponding to two different vertical end positions of the movable plate. In a first (downward) mode the movable plate stays in mechanical contact with the substrate whereas in a second (upward) mode an air cushion is generated in a chamber between the movable plate and the substrate for pressurizing the substrate onto the polishing pad.

Semiconductor substrate holder for chemical-mechanical polishing containing a movable plate

The method allows simultaneous polishing of a plurality of objects of a similar type, preferably silicon wafers. The polishing process is interrupted briefly at least once. During the polishing pause, the carriers on which the objects to be polished have been mounted are rotated onward sequentially and then the polishing operation is continued. The objects are mounted on one or more carriers which are at a free position during the polishing operation. This has the advantage that the polishing operation does not have to be additionally interrupted for the purpose of loading and unloading the carrier. This saves valuable machine time, so that the throughput is increased. At the same time, the fact that each wafer is processed at a plurality of polishing plates stabilizes the result of polishing, since the individual abrasion properties of the individual polishing plates are averaged out.

Method of simultaneously polishing a plurality of objects of a similar type, in particular silicon wafers, on a polishing installation

The invention describes a method for improving the readability of alignment marks on semiconductor wafers during multilayer metallization. Metal located in the alignment marks is etched back for the purpose of uncovering the edges of the alignment marks after the deposition of metal and subsequent CMP step. In the alternative, the oxide in the immediate vicinity of the alignment marks is etched back in a recess etching step until the metal in the alignment mark is partly uncovered.

Growing community of inventors

Dresden, Germany

Peter Lahnor