Intel Corporation

Microsoft Technology Licensing, LLC

Peter Lachner

Jason W Brandt

Konrad K Lai

Ravi Rajwar

Beeman C Strong

Laura A Knauth

Mayank Bomb

Robert Valentine

Gilbert A Neiger

Mark Jay Charney

Bret L Toll

Christopher J Hughes

Jesus Corbal

Martin Guy Dixon

Milind Baburao Girkar

Srinivas Chennupaty

Jonathan Cannon Hall

Rajesh S Parthasarathy

Chris J Newburn

Mark J Buxton

Jeffrey G Wiedemeier

Yen-Kuang (y K) Chen

Hideki (Saito) Ido

Matthew C Merten

Ofer Levy

Rolf H Kuehnis

Stephen J Robinson

Itamar S Kazachinsky

Ali-Reza Adl-Tabatabai

Gad Shlomo Sheaffer

Jan Stephen Gray

Charles P Roth

Martin Taillefer

Huy Van Nguyen

Tsvika Kurts

Kevin Safford

Hugh Wilkinson

Frank Binns

Darek Josip Mihocka

Michael Paulitsch

Riccardo Mariani

Peggy J Irelan

Tong Li

Jonathan Jay Tyler

Richard Wurdack

Thilo Schmitt

Thomas F Toll

Md Asifur Rahman

Maximillian Domeika

Michael P Rice

Gerold P Mueller

Thomas Toll

Evgueni V Brevnov

Riccardo Locatelli

Minesh S Desai

Uwe Schumacher

Andrej Tkalcec

Donald Korinke

Brevnov Evgueni V V

Maximillian J Domeika

In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.

System, apparatus and method for dynamic tracing in a system

System, apparatus and method for dynamic multi-source tracing in a system

A system to evaluate functional safety in an integrated circuit. The system includes a first circuit to execute an operation to cause to system to perform a function, where the function associated with a specified safety integrity level. The system also includes second circuit to capture trace data at an interface to the first circuit or at internal signals without inhibiting performance of the function, where the trace data comprising information that is used to determine whether the system can perform the function with an indicated level of functional safety and transmit the trace data to a safety evaluation circuit.

Functional safety over trace-and-debug

Herein is disclosed a multichip reference logging system comprising a control circuit, configured to generate a reference signal; a first chip, configured to generate a first operations log, the first chip further comprising a first reference circuit, configured to receive the reference signal and to create a first reference event in response to the received reference signal; a memory associated with the first chip, configured to store the first reference event within the first operations log; a second chip, configured to generate a second operations log, the second chip further comprising a second reference circuit, configured to receive the reference signal and to create a second reference event in response to the received reference signal; and a memory associated with the second chip, configured to store the second reference event within the second operations log.

Multichip reference logging synchronization

In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.

Tracking mode of a processing device in instruction tracing systems

According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

Gathering and scattering multiple data elements

In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

Last branch record indicators for transactional memory

A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.

Tracking deferred data packets in a debug trace architecture

In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.

Providing status of a processing device with periodic synchronization point in instruction tracing system

Last branch record register for storing taken branch information and transactional memory transaction indicator to be used in transaction execution analysis

A method is described that involves referring to first information from a directory table in system memory. The first information includes location information and size information of a first slice of system memory where first tracing data is to be stored. The method also includes tracking the amount of tracing data stored in the first slice of system memory and comparing the amount against the size information. The method also includes, before the first slice of system memory is filled, referring to second information from the directory table in system memory, where, the second information includes location information and size information of a second slice of system memory where second tracing data is to be stored. The first slice is not contiguous with the second slice of system memory.

Processor that records tracing data in non contiguous system memory slices

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing optional logging of debug activities in a real time instruction tracing log. For example, in one embodiment, such means may include an integrated circuit having means for initiating instruction tracing for instructions of a traced application, mode, or code region, as the instructions are executed by the integrated circuit; means for generating a plurality of packets to a debug log describing the instruction tracing; means for initiating an alternative mode of execution within the integrated circuit; and means for suppressing indication of entering the alternative mode of execution. Additional and alternative means may be implemented for selectively causing an integrated circuit to operate in accordance with an invisible trace mode or a visible trace mode upon transition to the alternative mode of execution.

Optional logging of debug activities in a real time instruction tracing log

Methods and apparatus relating to debugging parallel software using speculatively executed code sequences in a multiple core environment are described. In an embodiment, occurrence of a speculative code debug event is detected and a speculative code execution debug module is executed in response to occurrence of the event. Other embodiments are also disclosed and claimed.

Debugging parallel software using speculatively executed code sequences in a multiple core environment

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Heroldstatt, Germany

Peter Lachner