Infineon Technologies Ag

Intel Corporation

Intel Mobile Communications Gmbh

Lantiq Deutschland Gmbh

Peter Laaser

Armin Hanneberg

Andreas Wiesbauer

Peter Gregorius

Antonio Di Giandomenico

Thomas Blon

Dirk Friedrich

Christoph Schultz

Josef Holzleitner

Christian Duerdodt

Jens Kissing

Thomas Eichler

Carsten Eisenhut

Jeorg Hauptmann

Martin Gröpl

Examples provide an adaptation circuit and apparatus, method and computer programs for adapting, fabricating and operating, a radio transceiver, a mobile transceiver, a base station transceiver and storage for computer programs or instructions. The adaptation circuit () is configured to adapt a local oscillator signal in a radio transceiver (). The radio transceiver () comprises a transmission branch () and a reception branch (), which are subject to cross-talk. The reception branch () comprises a local oscillator () configured to generate the local oscillator signal. The adaptation circuit () comprises a control module () configured to determine crosstalk level information between the transmission branch () and the reception branch (), and to adapt the local oscillator signal based on the crosstalk level information.

Adaptation circuit for a transceiver

Radio frequency (RF) communication circuitry comprises an RF transceiver and conflict detection circuitry. The RF transceiver includes a first communication path configured to down-convert received RF signals using a first local oscillator (LO) receive frequency; and a second communication path configured to down-convert received RF signals using a second LO receive frequency and to operate simultaneously with the first communication path. The conflict detection circuitry is configured to determine path crosstalk using the first and second LO receive frequencies and using a first LO transmit frequency used by the first RF transceiver or a second RF transceiver to up-convert electrical signals for RF transmission, and initiate a change of the first LO receive frequency by a first frequency shift value and a change of the second LO receive frequency by a second frequency shift value in response to the path crosstalk.

Radio frequency transceiver with local oscillator control for multi-carrier applications

A system using multiple communication technologies for concurrent communication is disclosed. The system includes a transmitting subunit, a receiving subunit and a control unit. The transmitting subunit is configured to generate a transmit signal. The receiving subunit is configured to receive a receive signal. The control unit is coupled to the transmitting subunit and the receiving subunit and is configured to determine a presence or potential of crosstalk between the transmit signal and the receive signal. Additionally, the control unit is configured to reduce power of the transmitting subunit to mitigate the crosstalk.

Multi-standard systems and methods with interferer mitigation

A multi-standard transceiver includes a first subunit configured to perform signal processing according to a first communication standard and a second subunit configured to perform signal processing according to a second communication standard. Furthermore, the multi-standard transceiver includes an interference cancellation unit configured to drive an estimated interference signal from a first signal generated by the first subunit by performing the signal processing according to the first communication standard, and perform interference cancellation on a second signal generated by the second subunit by performing the signal processing according to the second communication standard based on the estimated interference signal.

Multi-standard transceiver, device and method

Embodiments related to analog front-ends for wireless and wired are described and depicted.

System and method for providing a versatile RF and analog front-end for wireless and wired networks

A circuit arrangement for signal mixing. One embodiment provides a circuit arrangement for mixing an input signal with at least one carrier signal. The circuit arrangement includes a current source and a current sink. The current source and the current sink have a mixer core coupled between them which provides cross-coupling between mixer input connections and mixer output connections.

Circuit arrangement for signal mixing

An amplifier stage includes a first and a second signal path having a series connection of a first transistor of a first conduction type which forms a control input for receiving an input signal to the amplifier stage and a second transistor of a second conduction type. The amplifier stage further includes a first and second signal output which are formed by a respective connection node of the respective first and second transistors. For each of the first and the second signal path, the amplifier stage includes a third transistor of the second conduction type which is connected to the respective second transistor as current mirror, and a fourth transistor of the first conduction type which is connected to the respective first transistor as a current mirror and which is for controlling the third transistor of the other signal path, respectively. Furthermore, for each of the first and the second signal path, a current source is provided with is connected in parallel to one of the respective first, second, third, and fourth transistors.

Amplifier stage, operational amplifier and method for amplifying a signal

A crest factor reduction circuit for reducing a crest factor (CF) of a multi-tone-data signal which is transmitted in a predetermined transmission frequency band, wherein the crest factor reduction circuit () comprises means () for subtracting a multi-tone-correction signal from said multi-tone-data signal, wherein the multi-tone-correction signal comprises a plurality of tone signals having frequencies outside said transmission frequency band.

Method and apparatus for reducing a crest factor of a multi-tone data signal

A line driver () for transmitting data with high bit rates, in particular for wire-bound data transmission in the full-duplex process, comprises a differential pair with differential pair transistors () for generating transmission impulses as a function of the data to be transmitted, whereby the transmission impulses are preferably output via cascode transistors (), each with the differential pair transistors () forming a cascode circuit, onto the data transmission line () connected to the line driver (). For reproducing the behaviour of the differential pair a replica differential pair with replica differential pair transistors () is provided, generating replica impulses corresponding to the transmission impulses, which replica impulses can be fed via replica cascode transistors () to a hybrid integrated circuit () for effecting echo compensation in relation to impulses received via the data transmission line ()

Line driver for transmitting data

A circuit arrangement for the analogue suppression of echoes, as in particular can be used in a hybrid-circuit for DSL-transmission systems, comprises a replica () for emulating the behaviour of the transmission line (). In addition, a circuit () for emulating the behaviour of the transmitter () is provided, which comprises at least one lowpass (). Furthermore, a replica () for emulating the behaviour of bridge taps () can also be provided, which comprises at least one bandpass (). Additionally, a replica () for emulating the behaviour of the line driver () can also be provided.

Circuit arrangement for the analogue suppression of echoes

A line driver which is especially suitable for wirebound data transmission at high bit rates, comprising several parallel-connected driver stages () respectively comprising a first pair of transistors consisting of two transistors () which are controlled in a differential manner according to digital data to be transmitted, and a second pair of transistors (). The transistors belonging to the second pair of transistors () are series-connected to a corresponding transistor () of the first pair of transistors. The individual driver stages () are connected by the transistors () of the second pair of transistors in a parallel manner to both the terminals of the line driver. Each driver stage () is associated with a control circuit () with transfer gates (), producing the differential control signals (VG, VG) for the two transistors () of the corresponding first pair of transistors.

Line driver

Sigma-delta A/D converter having at least one analog signal input ( ) for applying an analog input signal, a subtraction element ( ) having a plurality of capacitors ( ) for sampling the input signal during a sampling phase, it being possible during an integration phase to switch the capacitors ( ) to reference voltage sources ( ) depending on control signals, an integrator ( ) for integrating the output signal of the subtraction element ( ) during the integration phase, a quantizer ( ) for analog-to-digital conversion of the output signal of the integrator ( ) for outputting a digitized output signal to a digital signal output ( ), and having a control logic element ( ) for generating the control signals in such a way that the current load of the reference voltage sources ( ) is minimized during the integration phase.

Sigma-delta A/D converter

An amplifier output stage is described containing a preliminary stage, a final stage and a control device. The quiescent current that flows through transistors of the final stage is adjusted by the preliminary stage. For this, a current that is proportional to the quiescent current is generated in the control device from which control voltages are derived and controlled. The preliminary stage contains adjustable current sources for adjusting the quiescent current in a final step which are controlled by the control voltages.

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Munich, Germany

Peter Laaser