Tandem Computers Incorporated

Sun Microsystems, Inc.

Compaq Computer Corporation, Inc.

Peter L Fu

Mizanur Mohammed Rahman

Fred C Sabernick

Russell Mark Rector

Martin J Grosz

Jeff A Sprouse

Daniel E Lenoski

David J Garcia

Thomas M Wicki

Peter F Lai

Yongjun Zhang

Sachin Chopra

Von-Kyoung Kim

Jeff Sprouse

Hsiu-Nien Chen

Albert Jordan

Kong-Fal Woo

Srirarm Satakopan

A computer system configured to enhance data protection. A computer system includes one or more clients, such as processing subsystems and a memory subsystem interconnected via a network. Transactions within the system may involve the separation of data and a corresponding address in both space and time. At various points in the system, operations may be performed which seek to reunite a data and corresponding address, such as a store operation. In order to further ensure the correspondence of data and an address which is to be used in an operation, clients are configured to generate and utilize an additional symbol. The symbol is generated at least in part on an address which corresponds to data. The symbol is then associated with the data and serves to represent the corresponding address. The symbol may then be utilized by various clients within the system to check an address which is proposed to be used in an operation with the data.

Data and control integrity for transactions in a computer system

A method is described for protecting dirty data in cache memories in a cost-effective manner. When an instruction to write data to a memory location is received, and that memory location is being cached, the data is written to a plurality of cache lines, which are referred to as duplicate cache lines. When the data is written back to memory, one of the duplicate cache lines is read. If the cache line is not corrupt, it is written back to the appropriate memory location and marked available. In one embodiment, if more duplicate cache lines exist, they are invalidated. In another embodiment, the other corresponding cache lines may be read for the highest confidence of reliability, and then marked clean or invalid.

Dirty data protection for cache memories

Method and system for providing a netlist driven integrated router in a non-netlist driven environment for microprocessor designs includes retrieving top level netlist for the existing microprocessor design from the top level database and the design parameters for the new microprocessor design, and translating these netlist and design parameters at the front end so that the resulting data can be provided to an integrated router which is configured to generate re-routes for the new microprocessor design based on the top level netlist and the design parameters, where the generated re-routes are provided to a back end for translating the re-routes to new top level netlist and merging the new top level netlist with the existing top level netlist database.

Method and system for providing a netlist driven integrated router in a non-netlist driven environment

A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip. The maintenance diagnostic chip includes logic to halt either of the microprocessors if an error is detected, and read out the state of the microprocessors and a secondary cache attached to the microprocessors, before the state of the microprocessors at the time of the fault changes to a different state which might hide evidence of the cause of the fault.

Processor interface chip for dual-microprocessor processor system

Microprocessor interface apparatus having a boot address relocator, a

Method of state determination in lock-stepped processors

Disclosed is a circuit configuration that permits the monitoring of the operation of an input/output circuit of a digital unit under test by pseudo-random scan test techniques. A resistive element couples test signals to an input/output terminal of the device under test to which the input/output circuit is connected. The connection between the resistive element and the terminal is monitored during pseudo-random scan testing, permitting testing of the input/output circuitry.

Pseudo-Random scan test apparatus

A fixed entry-point map to produce an entry point address of a first micro-instruction for a particular macro-instruction. That address is then incremented by a fixed number to produce the second, third, etc. micro-instructions for that macro-instruction. In a first embodiment, after a fixed number of these address skips, the addresses are incremented by 1 so that successive micro-instructions are in adjacent address locations. In a second embodiment, the number of skips is variable.

Entry point mapping and skipping method and apparatus

A cross-coupled checking circuit is disclosed in which two identical integrated circuit chips are configured in a complementary manner and connected in parallel to the same inputs and outputs. One chip drives the data output data and the other chip drives the check symbol output corresponding to the output data. Each chip generates internal results and compares them to the output driven by the other chip.

Cross-coupled checking circuit

Growing community of inventors

Sunnyvale, CA, United States of America

Peter L Fu